EVERGREEN_CRTC_CONTROL 1387 drivers/gpu/drm/radeon/evergreen.c 	if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
EVERGREEN_CRTC_CONTROL 1682 drivers/gpu/drm/radeon/evergreen.c 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
EVERGREEN_CRTC_CONTROL 1684 drivers/gpu/drm/radeon/evergreen.c 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
EVERGREEN_CRTC_CONTROL 1707 drivers/gpu/drm/radeon/evergreen.c 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
EVERGREEN_CRTC_CONTROL 1709 drivers/gpu/drm/radeon/evergreen.c 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
EVERGREEN_CRTC_CONTROL 2679 drivers/gpu/drm/radeon/evergreen.c 		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
EVERGREEN_CRTC_CONTROL 2692 drivers/gpu/drm/radeon/evergreen.c 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
EVERGREEN_CRTC_CONTROL 2697 drivers/gpu/drm/radeon/evergreen.c 					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
EVERGREEN_CRTC_CONTROL 2721 drivers/gpu/drm/radeon/evergreen.c 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
EVERGREEN_CRTC_CONTROL 2723 drivers/gpu/drm/radeon/evergreen.c 			WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
EVERGREEN_CRTC_CONTROL 2827 drivers/gpu/drm/radeon/evergreen.c 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
EVERGREEN_CRTC_CONTROL 2830 drivers/gpu/drm/radeon/evergreen.c 				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
EVERGREEN_CRTC_CONTROL 3804 drivers/gpu/drm/radeon/evergreen.c 		if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
EVERGREEN_CRTC_CONTROL  675 drivers/gpu/drm/radeon/radeon_device.c 		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
EVERGREEN_CRTC_CONTROL  676 drivers/gpu/drm/radeon/radeon_device.c 			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
EVERGREEN_CRTC_CONTROL  678 drivers/gpu/drm/radeon/radeon_device.c 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
EVERGREEN_CRTC_CONTROL  679 drivers/gpu/drm/radeon/radeon_device.c 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
EVERGREEN_CRTC_CONTROL  682 drivers/gpu/drm/radeon/radeon_device.c 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
EVERGREEN_CRTC_CONTROL  683 drivers/gpu/drm/radeon/radeon_device.c 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);