EVERGREEN_CRTC4_REGISTER_OFFSET 2258 drivers/gpu/drm/radeon/atombios_crtc.c 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
EVERGREEN_CRTC4_REGISTER_OFFSET 6903 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
EVERGREEN_CRTC4_REGISTER_OFFSET 6916 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
EVERGREEN_CRTC4_REGISTER_OFFSET 7255 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
EVERGREEN_CRTC4_REGISTER_OFFSET 7272 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET 7324 drivers/gpu/drm/radeon/cik.c 			EVERGREEN_CRTC4_REGISTER_OFFSET);
EVERGREEN_CRTC4_REGISTER_OFFSET 7363 drivers/gpu/drm/radeon/cik.c 			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET 7369 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
EVERGREEN_CRTC4_REGISTER_OFFSET 7371 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
EVERGREEN_CRTC4_REGISTER_OFFSET  121 drivers/gpu/drm/radeon/evergreen.c 	EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET 1033 drivers/gpu/drm/radeon/evergreen_cs.c 		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET 1041 drivers/gpu/drm/radeon/evergreen_cs.c 		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET  682 drivers/gpu/drm/radeon/radeon_device.c 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
EVERGREEN_CRTC4_REGISTER_OFFSET 1508 drivers/gpu/drm/radeon/radeon_display.c 			EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET 1860 drivers/gpu/drm/radeon/radeon_display.c 				     EVERGREEN_CRTC4_REGISTER_OFFSET);
EVERGREEN_CRTC4_REGISTER_OFFSET 1862 drivers/gpu/drm/radeon/radeon_display.c 					  EVERGREEN_CRTC4_REGISTER_OFFSET);
EVERGREEN_CRTC4_REGISTER_OFFSET   21 drivers/gpu/drm/radeon/radeon_dp_mst.c 				       EVERGREEN_CRTC4_REGISTER_OFFSET,
EVERGREEN_CRTC4_REGISTER_OFFSET  152 drivers/gpu/drm/radeon/si.c 	EVERGREEN_CRTC4_REGISTER_OFFSET,