EVERGREEN_CRTC0_REGISTER_OFFSET 2246 drivers/gpu/drm/radeon/atombios_crtc.c 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
EVERGREEN_CRTC0_REGISTER_OFFSET 6896 drivers/gpu/drm/radeon/cik.c 	WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
EVERGREEN_CRTC0_REGISTER_OFFSET 6908 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
EVERGREEN_CRTC0_REGISTER_OFFSET 7248 drivers/gpu/drm/radeon/cik.c 	WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
EVERGREEN_CRTC0_REGISTER_OFFSET 7260 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET 7313 drivers/gpu/drm/radeon/cik.c 		EVERGREEN_CRTC0_REGISTER_OFFSET);
EVERGREEN_CRTC0_REGISTER_OFFSET 7330 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET 7336 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
EVERGREEN_CRTC0_REGISTER_OFFSET 7338 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
EVERGREEN_CRTC0_REGISTER_OFFSET  117 drivers/gpu/drm/radeon/evergreen.c 	EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET 1029 drivers/gpu/drm/radeon/evergreen_cs.c 		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET 1037 drivers/gpu/drm/radeon/evergreen_cs.c 		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET  675 drivers/gpu/drm/radeon/radeon_device.c 		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
EVERGREEN_CRTC0_REGISTER_OFFSET 1504 drivers/gpu/drm/radeon/radeon_display.c 			EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET 1832 drivers/gpu/drm/radeon/radeon_display.c 				     EVERGREEN_CRTC0_REGISTER_OFFSET);
EVERGREEN_CRTC0_REGISTER_OFFSET 1834 drivers/gpu/drm/radeon/radeon_display.c 					  EVERGREEN_CRTC0_REGISTER_OFFSET);
EVERGREEN_CRTC0_REGISTER_OFFSET   17 drivers/gpu/drm/radeon/radeon_dp_mst.c 	static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC0_REGISTER_OFFSET  148 drivers/gpu/drm/radeon/si.c 	EVERGREEN_CRTC0_REGISTER_OFFSET,