ETH_TXD1          230 drivers/pinctrl/actions/pinctrl-s700.c 	PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
ETH_TXD1          459 drivers/pinctrl/actions/pinctrl-s700.c static unsigned int  rgmii_txd1_mfp_pads[]		= { ETH_TXD1 };
ETH_TXD1          910 drivers/pinctrl/actions/pinctrl-s700.c 							    ETH_TXD1,
ETH_TXD1         1632 drivers/pinctrl/actions/pinctrl-s700.c static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
ETH_TXD1         1691 drivers/pinctrl/actions/pinctrl-s700.c 	[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
ETH_TXD1          210 drivers/pinctrl/actions/pinctrl-s900.c 	PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
ETH_TXD1          446 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_txd1_mfp_pads[]	= { ETH_TXD1 };
ETH_TXD1          805 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_tx_d0_d1_drv_pads[]	= { ETH_TXD0, ETH_TXD1 };
ETH_TXD1          855 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_tx_d0_d1_sr_pads[]	= { ETH_TXD0, ETH_TXD1 };
ETH_TXD1         1540 drivers/pinctrl/actions/pinctrl-s900.c static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
ETH_TXD1         1561 drivers/pinctrl/actions/pinctrl-s900.c 	[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
ETH_TXD1          804 drivers/pinctrl/sh-pfc/pfc-r8a77470.c 	PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
ETH_TXD1         1153 drivers/pinctrl/sh-pfc/pfc-r8a7778.c 	PINMUX_IPSR_GPSR(IP9_14_12,	ETH_TXD1),
ETH_TXD1         1207 drivers/pinctrl/sh-pfc/pfc-r8a7779.c 	PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
ETH_TXD1         1187 drivers/pinctrl/sh-pfc/pfc-r8a7790.c 	PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
ETH_TXD1         1475 drivers/pinctrl/sh-pfc/pfc-r8a7791.c 	PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
ETH_TXD1         1077 drivers/pinctrl/sh-pfc/pfc-r8a7794.c 	PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
ETH_TXD1          504 drivers/pinctrl/sh-pfc/pfc-sh7786.c 	GPIO_FN(ETH_TXD1),