ETH_RXD1          236 drivers/pinctrl/actions/pinctrl-s700.c 	PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
ETH_RXD1          479 drivers/pinctrl/actions/pinctrl-s700.c static unsigned int  rgmii_rxd1_mfp_pads[]		= { ETH_RXD1 };
ETH_RXD1          918 drivers/pinctrl/actions/pinctrl-s700.c 							    ETH_RXD1 };
ETH_RXD1         1629 drivers/pinctrl/actions/pinctrl-s700.c static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
ETH_RXD1         1695 drivers/pinctrl/actions/pinctrl-s700.c 	[ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
ETH_RXD1          214 drivers/pinctrl/actions/pinctrl-s900.c 	PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
ETH_RXD1          478 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_rxd1_mfp_pads[]	= { ETH_RXD1 };
ETH_RXD1          808 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_rx_d1_d0_drv_pads[]	= { ETH_RXD1, ETH_RXD0 };
ETH_RXD1          858 drivers/pinctrl/actions/pinctrl-s900.c static unsigned int rmii_rx_d1_d0_sr_pads[]	= { ETH_RXD1, ETH_RXD0 };
ETH_RXD1         1537 drivers/pinctrl/actions/pinctrl-s900.c static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
ETH_RXD1         1565 drivers/pinctrl/actions/pinctrl-s900.c 	[ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
ETH_RXD1          790 drivers/pinctrl/sh-pfc/pfc-r8a77470.c 	PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
ETH_RXD1         1183 drivers/pinctrl/sh-pfc/pfc-r8a7778.c 	PINMUX_IPSR_GPSR(IP9_29_27,	ETH_RXD1),
ETH_RXD1         1229 drivers/pinctrl/sh-pfc/pfc-r8a7779.c 	PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
ETH_RXD1         1166 drivers/pinctrl/sh-pfc/pfc-r8a7790.c 	PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
ETH_RXD1         1460 drivers/pinctrl/sh-pfc/pfc-r8a7791.c 	PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
ETH_RXD1         1060 drivers/pinctrl/sh-pfc/pfc-r8a7794.c 	PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
ETH_RXD1          532 drivers/pinctrl/sh-pfc/pfc-sh7786.c 	GPIO_FN(ETH_RXD1),