ETH_PLL_CTL0       76 drivers/net/phy/mdio-mux-meson-g12a.c 	val = readl(pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0       86 drivers/net/phy/mdio-mux-meson-g12a.c 	u32 val = readl(pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0       90 drivers/net/phy/mdio-mux-meson-g12a.c 	writel(val, pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0       94 drivers/net/phy/mdio-mux-meson-g12a.c 	writel(val, pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0      101 drivers/net/phy/mdio-mux-meson-g12a.c 	return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
ETH_PLL_CTL0      110 drivers/net/phy/mdio-mux-meson-g12a.c 	val = readl(pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0      113 drivers/net/phy/mdio-mux-meson-g12a.c 	writel(val, pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0      121 drivers/net/phy/mdio-mux-meson-g12a.c 	val = readl(pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0      131 drivers/net/phy/mdio-mux-meson-g12a.c 	writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
ETH_PLL_CTL0      258 drivers/net/phy/mdio-mux-meson-g12a.c 	mux->reg = priv->regs + ETH_PLL_CTL0;