AFMT_VBI_PACKET_CONTROL   91 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
AFMT_VBI_PACKET_CONTROL   98 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
AFMT_VBI_PACKET_CONTROL  102 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
AFMT_VBI_PACKET_CONTROL  103 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
AFMT_VBI_PACKET_CONTROL  136 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
AFMT_VBI_PACKET_CONTROL   60 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
AFMT_VBI_PACKET_CONTROL  119 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
AFMT_VBI_PACKET_CONTROL  120 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
AFMT_VBI_PACKET_CONTROL  121 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
AFMT_VBI_PACKET_CONTROL  649 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t AFMT_VBI_PACKET_CONTROL;
AFMT_VBI_PACKET_CONTROL   80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
AFMT_VBI_PACKET_CONTROL   87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
AFMT_VBI_PACKET_CONTROL   90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
AFMT_VBI_PACKET_CONTROL   91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
AFMT_VBI_PACKET_CONTROL  783 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
AFMT_VBI_PACKET_CONTROL  790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
AFMT_VBI_PACKET_CONTROL  793 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
AFMT_VBI_PACKET_CONTROL   46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
AFMT_VBI_PACKET_CONTROL  115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t AFMT_VBI_PACKET_CONTROL;
AFMT_VBI_PACKET_CONTROL  237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
AFMT_VBI_PACKET_CONTROL  241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
AFMT_VBI_PACKET_CONTROL  244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);
AFMT_VBI_PACKET_CONTROL  256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);