ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE  610 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE  837 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 5455 drivers/gpu/drm/radeon/cik.c 	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 5572 drivers/gpu/drm/radeon/cik.c 	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 2411 drivers/gpu/drm/radeon/evergreen.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 2494 drivers/gpu/drm/radeon/evergreen.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 1296 drivers/gpu/drm/radeon/ni.c 	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 1375 drivers/gpu/drm/radeon/ni.c 	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 1144 drivers/gpu/drm/radeon/r600.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 1236 drivers/gpu/drm/radeon/r600.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE  911 drivers/gpu/drm/radeon/rv770.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE  988 drivers/gpu/drm/radeon/rv770.c 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 4307 drivers/gpu/drm/radeon/si.c 	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 4393 drivers/gpu/drm/radeon/si.c 	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |