ENABLE_L1_TLB     121 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     302 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     117 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     290 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     600 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     721 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     827 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     965 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     147 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     347 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     103 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     280 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     171 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			    ENABLE_L1_TLB, 1);
ENABLE_L1_TLB     406 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 				    ENABLE_L1_TLB, 0);
ENABLE_L1_TLB     715 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	type ENABLE_L1_TLB;\
ENABLE_L1_TLB     808 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			ENABLE_L1_TLB, 1,
ENABLE_L1_TLB     382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
ENABLE_L1_TLB     572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	type ENABLE_L1_TLB;\
ENABLE_L1_TLB      73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			ENABLE_L1_TLB, 1,
ENABLE_L1_TLB     188 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 			ENABLE_L1_TLB, 1,
ENABLE_L1_TLB    5447 drivers/gpu/drm/radeon/cik.c 	       ENABLE_L1_TLB |
ENABLE_L1_TLB    2416 drivers/gpu/drm/radeon/evergreen.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB    2499 drivers/gpu/drm/radeon/evergreen.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB    1288 drivers/gpu/drm/radeon/ni.c 	       ENABLE_L1_TLB |
ENABLE_L1_TLB    1149 drivers/gpu/drm/radeon/r600.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB    1241 drivers/gpu/drm/radeon/r600.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB     916 drivers/gpu/drm/radeon/rv770.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB     993 drivers/gpu/drm/radeon/rv770.c 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
ENABLE_L1_TLB    4299 drivers/gpu/drm/radeon/si.c 	       ENABLE_L1_TLB |