ENABLE_INTR        65 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
ENABLE_INTR        85 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
ENABLE_INTR        65 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
ENABLE_INTR        85 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
ENABLE_INTR        50 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
ENABLE_INTR        67 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
ENABLE_INTR        38 drivers/gpu/drm/amd/amdgpu/si_ih.c 	ih_cntl |= ENABLE_INTR;
ENABLE_INTR        51 drivers/gpu/drm/amd/amdgpu/si_ih.c 	ih_cntl &= ~ENABLE_INTR;
ENABLE_INTR        65 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
ENABLE_INTR        82 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
ENABLE_INTR        52 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
ENABLE_INTR       108 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
ENABLE_INTR      6832 drivers/gpu/drm/radeon/cik.c 	ih_cntl |= ENABLE_INTR;
ENABLE_INTR      6852 drivers/gpu/drm/radeon/cik.c 	ih_cntl &= ~ENABLE_INTR;
ENABLE_INTR      3598 drivers/gpu/drm/radeon/r600.c 	ih_cntl |= ENABLE_INTR;
ENABLE_INTR      3611 drivers/gpu/drm/radeon/r600.c 	ih_cntl &= ~ENABLE_INTR;
ENABLE_INTR      5925 drivers/gpu/drm/radeon/si.c 	ih_cntl |= ENABLE_INTR;
ENABLE_INTR      5938 drivers/gpu/drm/radeon/si.c 	ih_cntl &= ~ENABLE_INTR;
ENABLE_INTR        61 drivers/irqchip/qcom-pdc.c 	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);