D_ALL 1971 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, D_ALL 1973 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, D_ALL 1976 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, D_ALL 1980 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, D_ALL 1982 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, D_ALL 1984 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, D_ALL 1987 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, D_ALL 1990 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, D_ALL 1993 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, D_ALL 1997 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 1, NULL}, D_ALL 2000 drivers/gpu/drm/i915/gvt/cmd_parser.c F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, D_ALL 2003 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, D_ALL 2006 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, D_ALL 2010 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 1, NULL}, D_ALL 2012 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, D_ALL 2015 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, D_ALL 2019 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, D_ALL 2022 drivers/gpu/drm/i915/gvt/cmd_parser.c R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)}, D_ALL 2024 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, D_ALL 2027 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL, CMD_LEN(0)}, D_ALL 2040 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, D_ALL 2044 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, cmd_handler_lri}, D_ALL 2050 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, D_ALL 2053 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, D_ALL 2056 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), D_ALL 2060 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6, D_ALL 2064 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, D_ALL 2068 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8, D_ALL 2072 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0, D_ALL 2076 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)}, D_ALL 2078 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2088 drivers/gpu/drm/i915/gvt/cmd_parser.c F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, D_ALL 2092 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, D_ALL 2096 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS | R_BCS, D_ALL, 0, 2, NULL}, D_ALL 2098 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2101 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2105 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, D_ALL 2107 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, D_ALL 2109 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2112 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2116 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2118 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2121 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2124 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2127 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2131 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, D_ALL 2133 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, D_ALL 2136 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, D_ALL 2139 drivers/gpu/drm/i915/gvt/cmd_parser.c R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, D_ALL 2143 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, D_ALL 2146 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_1(4), 8, NULL}, D_ALL 2149 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, D_ALL 2152 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_1(4), 8, NULL}, D_ALL 2155 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, D_ALL 2158 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, D_ALL 2162 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, D_ALL 2164 drivers/gpu/drm/i915/gvt/cmd_parser.c {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, D_ALL 2168 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, D_ALL 2172 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2176 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2180 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2184 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2188 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2192 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2196 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2200 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2204 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2208 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2212 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2216 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2220 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2224 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2226 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2229 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2232 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2235 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2239 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2242 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2245 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2248 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2251 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2254 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, D_ALL 2257 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, D_ALL 2260 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2263 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2266 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2269 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2272 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2275 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2278 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2281 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2284 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, D_ALL 2287 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, D_ALL 2290 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, D_ALL 2293 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, D_ALL 2296 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, D_ALL 2332 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2338 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 1, NULL}, D_ALL 2340 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2343 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2346 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2348 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2350 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2352 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2361 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2369 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2371 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2373 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2376 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2378 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2380 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2383 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2386 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2388 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2392 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_1(2), 8, NULL}, D_ALL 2395 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2398 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2401 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2404 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2407 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 8, NULL}, D_ALL 2410 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2416 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, ADDR_FIX_1(2), 8, NULL}, D_ALL 2419 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, D_ALL 2422 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2425 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2428 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2431 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2434 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2437 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2440 drivers/gpu/drm/i915/gvt/cmd_parser.c R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2443 drivers/gpu/drm/i915/gvt/cmd_parser.c D_ALL, 0, 9, NULL}, D_ALL 2462 drivers/gpu/drm/i915/gvt/cmd_parser.c {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2465 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2467 drivers/gpu/drm/i915/gvt/cmd_parser.c {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, D_ALL 2470 drivers/gpu/drm/i915/gvt/cmd_parser.c {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2473 drivers/gpu/drm/i915/gvt/cmd_parser.c {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2478 drivers/gpu/drm/i915/gvt/cmd_parser.c {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2481 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2483 drivers/gpu/drm/i915/gvt/cmd_parser.c {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, D_ALL 2492 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, D_ALL 2494 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2497 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2500 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2503 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, D_ALL 2505 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2508 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2511 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2514 drivers/gpu/drm/i915/gvt/cmd_parser.c {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, D_ALL 2517 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, D_ALL 2521 drivers/gpu/drm/i915/gvt/cmd_parser.c F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, D_ALL 2524 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2527 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2541 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2544 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2547 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2550 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2553 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2556 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2559 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 6, NULL}, D_ALL 2562 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2565 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2568 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2571 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2574 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2577 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2580 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2582 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2585 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2588 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, D_ALL 2591 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2594 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2597 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2600 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2603 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2606 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2609 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2612 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2615 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2618 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2621 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2623 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, D_ALL 2626 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, D_ALL 2628 drivers/gpu/drm/i915/gvt/cmd_parser.c {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, D_ALL 2631 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2634 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2637 drivers/gpu/drm/i915/gvt/cmd_parser.c R_VCS, D_ALL, 0, 12, NULL}, D_ALL 2639 drivers/gpu/drm/i915/gvt/cmd_parser.c {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, D_ALL 2641 drivers/gpu/drm/i915/gvt/cmd_parser.c {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, D_ALL 1864 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, D_ALL 1867 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); D_ALL 1868 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); D_ALL 1869 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); D_ALL 1870 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SDEISR, D_ALL); D_ALL 1872 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1877 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); D_ALL 1878 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); D_ALL 1879 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); D_ALL 1882 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1886 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1890 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); D_ALL 1894 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); D_ALL 1895 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); D_ALL 1896 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); D_ALL 1897 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN7_CXT_SIZE, D_ALL); D_ALL 1899 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1900 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1901 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1902 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); D_ALL 1903 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); D_ALL 1907 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, D_ALL 1911 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, D_ALL 1913 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, D_ALL 1915 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, D_ALL 1917 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, D_ALL 1920 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1921 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, D_ALL 1923 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1924 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1925 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1927 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1928 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1929 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1930 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, D_ALL 1932 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1933 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1934 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, D_ALL 1936 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, D_ALL 1938 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1939 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1940 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1941 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1942 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1943 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1944 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 1945 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1946 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1947 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 1950 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 1951 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x602a0), D_ALL); D_ALL 1953 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65050), D_ALL); D_ALL 1954 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x650b4), D_ALL); D_ALL 1956 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xc4040), D_ALL); D_ALL 1957 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DERRMR, D_ALL); D_ALL 1959 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(PIPE_A), D_ALL); D_ALL 1960 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(PIPE_B), D_ALL); D_ALL 1961 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(PIPE_C), D_ALL); D_ALL 1962 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); D_ALL 1964 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); D_ALL 1965 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); D_ALL 1966 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); D_ALL 1967 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); D_ALL 1969 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(PIPE_A), D_ALL); D_ALL 1970 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(PIPE_B), D_ALL); D_ALL 1971 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(PIPE_C), D_ALL); D_ALL 1972 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); D_ALL 1974 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); D_ALL 1975 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); D_ALL 1976 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); D_ALL 1977 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); D_ALL 1979 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); D_ALL 1980 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); D_ALL 1981 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); D_ALL 1982 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); D_ALL 1984 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURCNTR(PIPE_A), D_ALL); D_ALL 1985 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURCNTR(PIPE_B), D_ALL); D_ALL 1986 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURCNTR(PIPE_C), D_ALL); D_ALL 1988 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURPOS(PIPE_A), D_ALL); D_ALL 1989 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURPOS(PIPE_B), D_ALL); D_ALL 1990 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURPOS(PIPE_C), D_ALL); D_ALL 1992 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURBASE(PIPE_A), D_ALL); D_ALL 1993 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURBASE(PIPE_B), D_ALL); D_ALL 1994 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURBASE(PIPE_C), D_ALL); D_ALL 1996 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); D_ALL 1997 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); D_ALL 1998 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); D_ALL 2000 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x700ac), D_ALL); D_ALL 2001 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x710ac), D_ALL); D_ALL 2002 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x720ac), D_ALL); D_ALL 2004 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70090), D_ALL); D_ALL 2005 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70094), D_ALL); D_ALL 2006 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70098), D_ALL); D_ALL 2007 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7009c), D_ALL); D_ALL 2009 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPCNTR(PIPE_A), D_ALL); D_ALL 2010 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPADDR(PIPE_A), D_ALL); D_ALL 2011 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); D_ALL 2012 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPPOS(PIPE_A), D_ALL); D_ALL 2013 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSIZE(PIPE_A), D_ALL); D_ALL 2014 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); D_ALL 2015 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPOFFSET(PIPE_A), D_ALL); D_ALL 2016 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); D_ALL 2017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, D_ALL 2020 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPCNTR(PIPE_B), D_ALL); D_ALL 2021 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPADDR(PIPE_B), D_ALL); D_ALL 2022 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); D_ALL 2023 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPPOS(PIPE_B), D_ALL); D_ALL 2024 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSIZE(PIPE_B), D_ALL); D_ALL 2025 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); D_ALL 2026 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPOFFSET(PIPE_B), D_ALL); D_ALL 2027 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); D_ALL 2028 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, D_ALL 2031 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPCNTR(PIPE_C), D_ALL); D_ALL 2032 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPADDR(PIPE_C), D_ALL); D_ALL 2033 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); D_ALL 2034 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPPOS(PIPE_C), D_ALL); D_ALL 2035 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSIZE(PIPE_C), D_ALL); D_ALL 2036 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); D_ALL 2037 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPOFFSET(PIPE_C), D_ALL); D_ALL 2038 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); D_ALL 2039 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, D_ALL 2042 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRCTL(PIPE_A), D_ALL); D_ALL 2043 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRLINOFF(PIPE_A), D_ALL); D_ALL 2044 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); D_ALL 2045 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRPOS(PIPE_A), D_ALL); D_ALL 2046 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSIZE(PIPE_A), D_ALL); D_ALL 2047 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); D_ALL 2048 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); D_ALL 2049 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); D_ALL 2050 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); D_ALL 2051 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPROFFSET(PIPE_A), D_ALL); D_ALL 2052 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSCALE(PIPE_A), D_ALL); D_ALL 2053 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); D_ALL 2054 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, D_ALL 2057 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRCTL(PIPE_B), D_ALL); D_ALL 2058 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRLINOFF(PIPE_B), D_ALL); D_ALL 2059 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); D_ALL 2060 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRPOS(PIPE_B), D_ALL); D_ALL 2061 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSIZE(PIPE_B), D_ALL); D_ALL 2062 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); D_ALL 2063 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); D_ALL 2064 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); D_ALL 2065 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); D_ALL 2066 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPROFFSET(PIPE_B), D_ALL); D_ALL 2067 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSCALE(PIPE_B), D_ALL); D_ALL 2068 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); D_ALL 2069 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, D_ALL 2072 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRCTL(PIPE_C), D_ALL); D_ALL 2073 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRLINOFF(PIPE_C), D_ALL); D_ALL 2074 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); D_ALL 2075 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRPOS(PIPE_C), D_ALL); D_ALL 2076 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSIZE(PIPE_C), D_ALL); D_ALL 2077 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); D_ALL 2078 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); D_ALL 2079 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); D_ALL 2080 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); D_ALL 2081 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPROFFSET(PIPE_C), D_ALL); D_ALL 2082 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSCALE(PIPE_C), D_ALL); D_ALL 2083 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); D_ALL 2084 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, D_ALL 2087 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); D_ALL 2088 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HBLANK(TRANSCODER_A), D_ALL); D_ALL 2089 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSYNC(TRANSCODER_A), D_ALL); D_ALL 2090 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); D_ALL 2091 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VBLANK(TRANSCODER_A), D_ALL); D_ALL 2092 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNC(TRANSCODER_A), D_ALL); D_ALL 2093 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); D_ALL 2094 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); D_ALL 2095 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); D_ALL 2097 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); D_ALL 2098 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HBLANK(TRANSCODER_B), D_ALL); D_ALL 2099 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSYNC(TRANSCODER_B), D_ALL); D_ALL 2100 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); D_ALL 2101 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VBLANK(TRANSCODER_B), D_ALL); D_ALL 2102 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNC(TRANSCODER_B), D_ALL); D_ALL 2103 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); D_ALL 2104 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); D_ALL 2105 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); D_ALL 2107 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); D_ALL 2108 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HBLANK(TRANSCODER_C), D_ALL); D_ALL 2109 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSYNC(TRANSCODER_C), D_ALL); D_ALL 2110 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); D_ALL 2111 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VBLANK(TRANSCODER_C), D_ALL); D_ALL 2112 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNC(TRANSCODER_C), D_ALL); D_ALL 2113 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); D_ALL 2114 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); D_ALL 2115 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); D_ALL 2117 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); D_ALL 2118 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); D_ALL 2119 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); D_ALL 2120 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); D_ALL 2121 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); D_ALL 2122 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); D_ALL 2123 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); D_ALL 2124 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); D_ALL 2126 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); D_ALL 2127 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); D_ALL 2128 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); D_ALL 2129 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); D_ALL 2130 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); D_ALL 2131 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); D_ALL 2132 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); D_ALL 2133 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); D_ALL 2135 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); D_ALL 2136 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); D_ALL 2137 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); D_ALL 2138 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); D_ALL 2139 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); D_ALL 2140 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); D_ALL 2141 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); D_ALL 2142 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); D_ALL 2144 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); D_ALL 2145 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); D_ALL 2146 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); D_ALL 2147 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); D_ALL 2148 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); D_ALL 2149 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); D_ALL 2150 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); D_ALL 2151 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); D_ALL 2153 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); D_ALL 2154 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); D_ALL 2155 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); D_ALL 2156 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); D_ALL 2157 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); D_ALL 2158 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); D_ALL 2159 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); D_ALL 2160 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); D_ALL 2162 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_CTL(PIPE_A), D_ALL); D_ALL 2163 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); D_ALL 2164 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); D_ALL 2165 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_VSCALE(PIPE_A), D_ALL); D_ALL 2166 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_HSCALE(PIPE_A), D_ALL); D_ALL 2168 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_CTL(PIPE_B), D_ALL); D_ALL 2169 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); D_ALL 2170 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); D_ALL 2171 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_VSCALE(PIPE_B), D_ALL); D_ALL 2172 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_HSCALE(PIPE_B), D_ALL); D_ALL 2174 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_CTL(PIPE_C), D_ALL); D_ALL 2175 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); D_ALL 2176 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); D_ALL 2177 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_VSCALE(PIPE_C), D_ALL); D_ALL 2178 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_HSCALE(PIPE_C), D_ALL); D_ALL 2180 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM0_PIPEA_ILK, D_ALL); D_ALL 2181 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM0_PIPEB_ILK, D_ALL); D_ALL 2182 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM0_PIPEC_IVB, D_ALL); D_ALL 2183 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM1_LP_ILK, D_ALL); D_ALL 2184 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM2_LP_ILK, D_ALL); D_ALL 2185 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM3_LP_ILK, D_ALL); D_ALL 2186 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM1S_LP_ILK, D_ALL); D_ALL 2187 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM2S_LP_IVB, D_ALL); D_ALL 2188 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(WM3S_LP_IVB, D_ALL); D_ALL 2190 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); D_ALL 2191 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BLC_PWM_CPU_CTL, D_ALL); D_ALL 2192 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); D_ALL 2193 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); D_ALL 2195 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x48268), D_ALL); D_ALL 2197 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, D_ALL 2199 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); D_ALL 2200 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2211 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); D_ALL 2212 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); D_ALL 2214 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); D_ALL 2215 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); D_ALL 2216 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); D_ALL 2217 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2218 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2219 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2220 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2221 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2222 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); D_ALL 2224 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); D_ALL 2225 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); D_ALL 2226 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); D_ALL 2227 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); D_ALL 2228 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); D_ALL 2229 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); D_ALL 2230 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); D_ALL 2232 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); D_ALL 2233 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); D_ALL 2234 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); D_ALL 2235 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); D_ALL 2236 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); D_ALL 2237 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); D_ALL 2238 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); D_ALL 2240 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); D_ALL 2241 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); D_ALL 2242 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); D_ALL 2243 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); D_ALL 2244 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); D_ALL 2245 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); D_ALL 2246 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); D_ALL 2247 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); D_ALL 2249 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); D_ALL 2250 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); D_ALL 2251 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); D_ALL 2253 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); D_ALL 2254 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); D_ALL 2255 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); D_ALL 2257 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); D_ALL 2258 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); D_ALL 2259 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); D_ALL 2261 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); D_ALL 2262 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); D_ALL 2263 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); D_ALL 2265 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); D_ALL 2266 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); D_ALL 2267 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); D_ALL 2268 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); D_ALL 2269 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); D_ALL 2270 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); D_ALL 2272 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); D_ALL 2273 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_PP_DIVISOR, D_ALL); D_ALL 2274 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_PP_STATUS, D_ALL); D_ALL 2275 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_LVDS, D_ALL); D_ALL 2276 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); D_ALL 2277 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); D_ALL 2278 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPA0), D_ALL); D_ALL 2279 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPA1), D_ALL); D_ALL 2280 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPB0), D_ALL); D_ALL 2281 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPB1), D_ALL); D_ALL 2282 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_DREF_CONTROL, D_ALL); D_ALL 2283 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_RAWCLK_FREQ, D_ALL); D_ALL 2284 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_DPLL_SEL, D_ALL); D_ALL 2286 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x61208), D_ALL); D_ALL 2287 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6120c), D_ALL); D_ALL 2288 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_PP_ON_DELAYS, D_ALL); D_ALL 2289 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); D_ALL 2291 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2292 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2293 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2294 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2295 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2296 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); D_ALL 2298 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, D_ALL 2305 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); D_ALL 2306 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(FUSE_STRAP, D_ALL); D_ALL 2307 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); D_ALL 2309 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DISP_ARB_CTL, D_ALL); D_ALL 2310 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DISP_ARB_CTL2, D_ALL); D_ALL 2312 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); D_ALL 2313 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); D_ALL 2314 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); D_ALL 2316 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SOUTH_CHICKEN1, D_ALL); D_ALL 2317 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); D_ALL 2318 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); D_ALL 2319 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); D_ALL 2320 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); D_ALL 2321 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); D_ALL 2322 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); D_ALL 2324 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_CB_BASE, D_ALL); D_ALL 2325 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_CONTROL, D_ALL); D_ALL 2326 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); D_ALL 2327 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_STATUS, D_ALL); D_ALL 2328 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); D_ALL 2329 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_DPFC_CHICKEN, D_ALL); D_ALL 2330 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ILK_FBC_RT_BASE, D_ALL); D_ALL 2332 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(IPS_CTL, D_ALL); D_ALL 2334 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); D_ALL 2335 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); D_ALL 2336 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); D_ALL 2337 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); D_ALL 2338 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); D_ALL 2339 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); D_ALL 2340 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); D_ALL 2341 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); D_ALL 2342 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); D_ALL 2343 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); D_ALL 2344 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); D_ALL 2345 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); D_ALL 2346 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); D_ALL 2348 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); D_ALL 2349 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); D_ALL 2350 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); D_ALL 2351 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); D_ALL 2352 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); D_ALL 2353 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); D_ALL 2354 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); D_ALL 2355 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); D_ALL 2356 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); D_ALL 2357 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); D_ALL 2358 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); D_ALL 2359 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); D_ALL 2360 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); D_ALL 2362 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); D_ALL 2363 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); D_ALL 2364 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); D_ALL 2365 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); D_ALL 2366 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); D_ALL 2367 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); D_ALL 2368 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); D_ALL 2369 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); D_ALL 2370 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); D_ALL 2371 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); D_ALL 2372 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); D_ALL 2373 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); D_ALL 2374 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); D_ALL 2376 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); D_ALL 2377 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); D_ALL 2378 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2380 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); D_ALL 2381 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); D_ALL 2382 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2384 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); D_ALL 2385 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); D_ALL 2386 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2388 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x60110), D_ALL); D_ALL 2389 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x61110), D_ALL); D_ALL 2390 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2391 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2392 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2400 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); D_ALL 2401 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); D_ALL 2402 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); D_ALL 2403 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPLL_CTL, D_ALL); D_ALL 2404 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); D_ALL 2405 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); D_ALL 2406 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); D_ALL 2407 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); D_ALL 2408 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); D_ALL 2409 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); D_ALL 2410 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); D_ALL 2411 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); D_ALL 2412 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); D_ALL 2413 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); D_ALL 2415 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); D_ALL 2416 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x46508), D_ALL); D_ALL 2418 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49080), D_ALL); D_ALL 2419 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49180), D_ALL); D_ALL 2420 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49280), D_ALL); D_ALL 2422 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2423 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2424 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2426 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); D_ALL 2427 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); D_ALL 2428 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); D_ALL 2430 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_MULT(PIPE_A), D_ALL); D_ALL 2431 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_MULT(PIPE_B), D_ALL); D_ALL 2432 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_MULT(PIPE_C), D_ALL); D_ALL 2434 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); D_ALL 2435 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); D_ALL 2436 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); D_ALL 2438 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); D_ALL 2439 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SBI_ADDR, D_ALL); D_ALL 2440 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); D_ALL 2441 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); D_ALL 2442 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIXCLK_GATE, D_ALL); D_ALL 2444 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, D_ALL 2447 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); D_ALL 2448 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); D_ALL 2449 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); D_ALL 2450 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); D_ALL 2451 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); D_ALL 2453 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); D_ALL 2454 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); D_ALL 2455 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); D_ALL 2456 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); D_ALL 2457 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); D_ALL 2459 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); D_ALL 2460 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); D_ALL 2461 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); D_ALL 2462 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); D_ALL 2463 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); D_ALL 2465 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2466 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2467 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2468 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2469 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2471 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); D_ALL 2472 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); D_ALL 2473 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); D_ALL 2475 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); D_ALL 2476 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); D_ALL 2477 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); D_ALL 2478 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); D_ALL 2480 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); D_ALL 2481 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); D_ALL 2482 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); D_ALL 2483 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); D_ALL 2485 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); D_ALL 2486 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(FORCEWAKE_ACK, D_ALL); D_ALL 2487 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); D_ALL 2488 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); D_ALL 2489 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2490 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2493 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ECOBUS, D_ALL); D_ALL 2494 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); D_ALL 2495 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); D_ALL 2496 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RPNSWREQ, D_ALL); D_ALL 2497 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); D_ALL 2498 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); D_ALL 2499 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); D_ALL 2500 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RPSTAT1, D_ALL); D_ALL 2501 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_CONTROL, D_ALL); D_ALL 2502 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); D_ALL 2503 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); D_ALL 2504 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); D_ALL 2505 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_CUR_UP, D_ALL); D_ALL 2506 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_PREV_UP, D_ALL); D_ALL 2507 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); D_ALL 2508 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); D_ALL 2509 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); D_ALL 2510 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_UP_EI, D_ALL); D_ALL 2511 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_DOWN_EI, D_ALL); D_ALL 2512 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); D_ALL 2513 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); D_ALL 2514 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); D_ALL 2515 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); D_ALL 2516 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); D_ALL 2517 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); D_ALL 2518 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC_SLEEP, D_ALL); D_ALL 2519 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); D_ALL 2520 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); D_ALL 2521 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); D_ALL 2522 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); D_ALL 2523 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_PMINTRMSK, D_ALL); D_ALL 2531 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(RSTDBYCTL, D_ALL); D_ALL 2533 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); D_ALL 2534 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); D_ALL 2535 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); D_ALL 2537 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TILECTL, D_ALL); D_ALL 2539 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_UCGCTL1, D_ALL); D_ALL 2540 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_UCGCTL2, D_ALL); D_ALL 2542 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); D_ALL 2544 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_PCODE_DATA, D_ALL); D_ALL 2545 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x13812c), D_ALL); D_ALL 2546 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); D_ALL 2547 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_EDRAM_CAP, D_ALL); D_ALL 2548 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_IDICR, D_ALL); D_ALL 2549 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); D_ALL 2551 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x3c), D_ALL); D_ALL 2552 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x860), D_ALL); D_ALL 2553 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(ECOSKPD, D_ALL); D_ALL 2554 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x121d0), D_ALL); D_ALL 2555 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); D_ALL 2556 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x41d0), D_ALL); D_ALL 2557 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAC_ECO_BITS, D_ALL); D_ALL 2558 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6200), D_ALL); D_ALL 2559 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6204), D_ALL); D_ALL 2560 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6208), D_ALL); D_ALL 2561 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7118), D_ALL); D_ALL 2562 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7180), D_ALL); D_ALL 2563 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7408), D_ALL); D_ALL 2564 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7c00), D_ALL); D_ALL 2565 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); D_ALL 2566 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x911c), D_ALL); D_ALL 2567 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x9120), D_ALL); D_ALL 2568 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2570 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAB_CTL, D_ALL); D_ALL 2571 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x48800), D_ALL); D_ALL 2572 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xce044), D_ALL); D_ALL 2573 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6500), D_ALL); D_ALL 2574 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6504), D_ALL); D_ALL 2575 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6600), D_ALL); D_ALL 2576 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6604), D_ALL); D_ALL 2577 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6700), D_ALL); D_ALL 2578 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6704), D_ALL); D_ALL 2579 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6800), D_ALL); D_ALL 2580 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6804), D_ALL); D_ALL 2581 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_GMBUS4, D_ALL); D_ALL 2582 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PCH_GMBUS5, D_ALL); D_ALL 2584 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x902c), D_ALL); D_ALL 2585 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008), D_ALL); D_ALL 2586 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c), D_ALL); D_ALL 2587 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); D_ALL 2588 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); D_ALL 2589 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); D_ALL 2590 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); D_ALL 2591 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); D_ALL 2592 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); D_ALL 2593 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408), D_ALL); D_ALL 2594 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c), D_ALL); D_ALL 2595 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); D_ALL 2596 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); D_ALL 2597 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); D_ALL 2598 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); D_ALL 2599 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); D_ALL 2600 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); D_ALL 2601 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc810), D_ALL); D_ALL 2602 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc81c), D_ALL); D_ALL 2603 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc828), D_ALL); D_ALL 2604 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc834), D_ALL); D_ALL 2605 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc00), D_ALL); D_ALL 2606 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc0c), D_ALL); D_ALL 2607 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc18), D_ALL); D_ALL 2608 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc24), D_ALL); D_ALL 2609 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd000), D_ALL); D_ALL 2610 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd00c), D_ALL); D_ALL 2611 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd018), D_ALL); D_ALL 2612 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd024), D_ALL); D_ALL 2613 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd034), D_ALL); D_ALL 2615 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); D_ALL 2616 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x2054), D_ALL); D_ALL 2617 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x12054), D_ALL); D_ALL 2618 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x22054), D_ALL); D_ALL 2619 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x1a054), D_ALL); D_ALL 2621 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x44070), D_ALL); D_ALL 2623 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2624 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2625 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2626 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2631 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2632 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2633 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2637 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2639 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2640 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2641 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2642 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2643 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2644 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2645 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2646 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2647 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2648 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2649 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); D_ALL 2657 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); D_ALL 2658 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); D_ALL 2659 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2660 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2661 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2662 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 2663 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); D_ALL 3329 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, D_ALL 3330 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, D_ALL 3332 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, D_ALL 3333 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, D_ALL 3334 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},