DSS_CONTROL       403 arch/arm/mach-omap2/display.c 	omap_hwmod_write(0x0, oh, DSS_CONTROL);
DSS_CONTROL       367 drivers/gpu/drm/omapdrm/dss/dss.c 	DUMPREG(dss, DSS_CONTROL);
DSS_CONTROL       431 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, b,		/* DISPC_CLK_SWITCH */
DSS_CONTROL       461 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos);	/* DSIx_CLK_SWITCH */
DSS_CONTROL       481 drivers/gpu/drm/omapdrm/dss/dss.c 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
DSS_CONTROL       489 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
DSS_CONTROL       513 drivers/gpu/drm/omapdrm/dss/dss.c 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
DSS_CONTROL       520 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
DSS_CONTROL       542 drivers/gpu/drm/omapdrm/dss/dss.c 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
DSS_CONTROL       549 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
DSS_CONTROL       709 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
DSS_CONTROL       715 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
DSS_CONTROL       733 drivers/gpu/drm/omapdrm/dss/dss.c 		REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
DSS_CONTROL       761 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
DSS_CONTROL       788 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
DSS_CONTROL      1372 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
DSS_CONTROL      1377 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
DSS_CONTROL      1378 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
DSS_CONTROL      1379 drivers/gpu/drm/omapdrm/dss/dss.c 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
DSS_CONTROL       382 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	DUMPREG(DSS_CONTROL);
DSS_CONTROL       417 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, b, start, end);	/* DISPC_CLK_SWITCH */
DSS_CONTROL       445 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, b, pos, pos);	/* DSIx_CLK_SWITCH */
DSS_CONTROL       480 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, b, pos, pos);	/* LCDx_CLK_SWITCH */
DSS_CONTROL       616 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
DSS_CONTROL       621 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
DSS_CONTROL       635 drivers/video/fbdev/omap2/omapfb/dss/dss.c 		REG_FLD_MOD(DSS_CONTROL, src, 15, 15);	/* VENC_HDMI_SWITCH */
DSS_CONTROL       649 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	return REG_GET(DSS_CONTROL, 15, 15);
DSS_CONTROL       675 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
DSS_CONTROL       701 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
DSS_CONTROL      1118 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
DSS_CONTROL      1123 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
DSS_CONTROL      1124 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
DSS_CONTROL      1125 drivers/video/fbdev/omap2/omapfb/dss/dss.c 	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */