DSPSURF          3835 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE_FW(DSPSURF(i9xx_plane),
DSPSURF          3870 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
DSPSURF          8640 drivers/gpu/drm/i915/display/intel_display.c 		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
DSPSURF          8646 drivers/gpu/drm/i915/display/intel_display.c 		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
DSPSURF          17257 drivers/gpu/drm/i915/display/intel_display.c 			error->plane[i].surface = I915_READ(DSPSURF(i));
DSPSURF          1245 drivers/gpu/drm/i915/gvt/cmd_parser.c 		info->surf_reg = DSPSURF(info->pipe);
DSPSURF          1311 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->surf_reg = DSPSURF(info->pipe);
DSPSURF           247 drivers/gpu/drm/i915/gvt/fb_decoder.c 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
DSPSURF           749 drivers/gpu/drm/i915/gvt/handlers.c 	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
DSPSURF          2014 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
DSPSURF          2025 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
DSPSURF          2036 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
DSPSURF          8901 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
DSPSURF          8902 drivers/gpu/drm/i915/intel_pm.c 		POSTING_READ(DSPSURF(pipe));