DSC_SF 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ DSC_SF 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ DSC_SF 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ DSC_SF 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ DSC_SF 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ DSC_SF 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ DSC_SF 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ DSC_SF 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ DSC_SF 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \ DSC_SF 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \ DSC_SF 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \ DSC_SF 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \ DSC_SF 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \ DSC_SF 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \ DSC_SF 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \ DSC_SF 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \ DSC_SF 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \ DSC_SF 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \ DSC_SF 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \ DSC_SF 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \ DSC_SF 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \ DSC_SF 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \ DSC_SF 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \ DSC_SF 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \ DSC_SF 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \ DSC_SF 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \ DSC_SF 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \ DSC_SF 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \ DSC_SF 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \ DSC_SF 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \ DSC_SF 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \ DSC_SF 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \ DSC_SF 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \ DSC_SF 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \ DSC_SF 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \ DSC_SF 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \ DSC_SF 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \ DSC_SF 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \ DSC_SF 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \ DSC_SF 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \ DSC_SF 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \ DSC_SF 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \ DSC_SF 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \ DSC_SF 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \ DSC_SF 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \ DSC_SF 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \ DSC_SF 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \ DSC_SF 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \ DSC_SF 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \ DSC_SF 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \ DSC_SF 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \ DSC_SF 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \ DSC_SF 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \ DSC_SF 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \ DSC_SF 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \ DSC_SF 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \ DSC_SF 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \ DSC_SF 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \ DSC_SF 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \ DSC_SF 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \ DSC_SF 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \ DSC_SF 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \ DSC_SF 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \ DSC_SF 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \ DSC_SF 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \ DSC_SF 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \ DSC_SF 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \ DSC_SF 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \ DSC_SF 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \ DSC_SF 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \ DSC_SF 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \ DSC_SF 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \ DSC_SF 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \ DSC_SF 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \ DSC_SF 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \ DSC_SF 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \ DSC_SF 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \ DSC_SF 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \ DSC_SF 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \ DSC_SF 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \ DSC_SF 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \ DSC_SF 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \ DSC_SF 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \ DSC_SF 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \ DSC_SF 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \ DSC_SF 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \ DSC_SF 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \ DSC_SF 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \ DSC_SF 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \ DSC_SF 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \ DSC_SF 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \ DSC_SF 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \ DSC_SF 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \ DSC_SF 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \ DSC_SF 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \ DSC_SF 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \ DSC_SF 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \ DSC_SF 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \ DSC_SF 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \ DSC_SF 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \ DSC_SF 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \ DSC_SF 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \ DSC_SF 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \ DSC_SF 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \ DSC_SF 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \ DSC_SF 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \ DSC_SF 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \ DSC_SF 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \ DSC_SF 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \ DSC_SF 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \ DSC_SF 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \ DSC_SF 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \ DSC_SF 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \ DSC_SF 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \ DSC_SF 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \ DSC_SF 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \ DSC_SF 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \ DSC_SF 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \ DSC_SF 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \ DSC_SF 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \ DSC_SF 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \ DSC_SF 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \ DSC_SF 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \ DSC_SF 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \ DSC_SF 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \ DSC_SF 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \ DSC_SF 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \ DSC_SF 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \ DSC_SF 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \ DSC_SF 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \ DSC_SF 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \ DSC_SF 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \ DSC_SF 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \ DSC_SF 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \ DSC_SF 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ DSC_SF 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \ DSC_SF 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \ DSC_SF 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ DSC_SF 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)