DRA7XX_PRM_CKGEN_INST 98 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) DRA7XX_PRM_CKGEN_INST 100 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) DRA7XX_PRM_CKGEN_INST 102 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) DRA7XX_PRM_CKGEN_INST 104 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) DRA7XX_PRM_CKGEN_INST 106 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) DRA7XX_PRM_CKGEN_INST 108 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) DRA7XX_PRM_CKGEN_INST 110 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) DRA7XX_PRM_CKGEN_INST 112 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) DRA7XX_PRM_CKGEN_INST 114 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) DRA7XX_PRM_CKGEN_INST 116 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) DRA7XX_PRM_CKGEN_INST 118 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) DRA7XX_PRM_CKGEN_INST 120 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) DRA7XX_PRM_CKGEN_INST 122 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) DRA7XX_PRM_CKGEN_INST 124 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) DRA7XX_PRM_CKGEN_INST 126 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) DRA7XX_PRM_CKGEN_INST 128 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) DRA7XX_PRM_CKGEN_INST 130 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) DRA7XX_PRM_CKGEN_INST 132 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) DRA7XX_PRM_CKGEN_INST 134 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) DRA7XX_PRM_CKGEN_INST 136 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) DRA7XX_PRM_CKGEN_INST 138 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) DRA7XX_PRM_CKGEN_INST 140 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) DRA7XX_PRM_CKGEN_INST 142 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) DRA7XX_PRM_CKGEN_INST 144 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) DRA7XX_PRM_CKGEN_INST 146 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) DRA7XX_PRM_CKGEN_INST 148 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) DRA7XX_PRM_CKGEN_INST 150 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) DRA7XX_PRM_CKGEN_INST 152 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) DRA7XX_PRM_CKGEN_INST 154 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) DRA7XX_PRM_CKGEN_INST 156 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) DRA7XX_PRM_CKGEN_INST 158 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) DRA7XX_PRM_CKGEN_INST 160 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) DRA7XX_PRM_CKGEN_INST 162 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) DRA7XX_PRM_CKGEN_INST 164 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) DRA7XX_PRM_CKGEN_INST 166 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) DRA7XX_PRM_CKGEN_INST 168 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) DRA7XX_PRM_CKGEN_INST 170 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) DRA7XX_PRM_CKGEN_INST 172 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) DRA7XX_PRM_CKGEN_INST 174 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) DRA7XX_PRM_CKGEN_INST 176 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) DRA7XX_PRM_CKGEN_INST 178 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) DRA7XX_PRM_CKGEN_INST 180 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) DRA7XX_PRM_CKGEN_INST 182 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) DRA7XX_PRM_CKGEN_INST 184 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) DRA7XX_PRM_CKGEN_INST 186 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) DRA7XX_PRM_CKGEN_INST 188 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) DRA7XX_PRM_CKGEN_INST 190 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) DRA7XX_PRM_CKGEN_INST 192 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) DRA7XX_PRM_CKGEN_INST 194 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) DRA7XX_PRM_CKGEN_INST 196 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) DRA7XX_PRM_CKGEN_INST 198 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) DRA7XX_PRM_CKGEN_INST 200 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) DRA7XX_PRM_CKGEN_INST 202 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) DRA7XX_PRM_CKGEN_INST 204 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)