DRA7XX_CM_CORE_REGADDR 69 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 74 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) DRA7XX_CM_CORE_REGADDR 76 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) DRA7XX_CM_CORE_REGADDR 78 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 80 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) DRA7XX_CM_CORE_REGADDR 82 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) DRA7XX_CM_CORE_REGADDR 84 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) DRA7XX_CM_CORE_REGADDR 86 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) DRA7XX_CM_CORE_REGADDR 88 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) DRA7XX_CM_CORE_REGADDR 90 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) DRA7XX_CM_CORE_REGADDR 92 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) DRA7XX_CM_CORE_REGADDR 94 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) DRA7XX_CM_CORE_REGADDR 98 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) DRA7XX_CM_CORE_REGADDR 100 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) DRA7XX_CM_CORE_REGADDR 102 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) DRA7XX_CM_CORE_REGADDR 104 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) DRA7XX_CM_CORE_REGADDR 106 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) DRA7XX_CM_CORE_REGADDR 110 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) DRA7XX_CM_CORE_REGADDR 112 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) DRA7XX_CM_CORE_REGADDR 114 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) DRA7XX_CM_CORE_REGADDR 116 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) DRA7XX_CM_CORE_REGADDR 118 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) DRA7XX_CM_CORE_REGADDR 120 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) DRA7XX_CM_CORE_REGADDR 124 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) DRA7XX_CM_CORE_REGADDR 126 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) DRA7XX_CM_CORE_REGADDR 128 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) DRA7XX_CM_CORE_REGADDR 130 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) DRA7XX_CM_CORE_REGADDR 135 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 137 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) DRA7XX_CM_CORE_REGADDR 139 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 141 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) DRA7XX_CM_CORE_REGADDR 143 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) DRA7XX_CM_CORE_REGADDR 145 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) DRA7XX_CM_CORE_REGADDR 147 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) DRA7XX_CM_CORE_REGADDR 149 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) DRA7XX_CM_CORE_REGADDR 151 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) DRA7XX_CM_CORE_REGADDR 153 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) DRA7XX_CM_CORE_REGADDR 155 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) DRA7XX_CM_CORE_REGADDR 157 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) DRA7XX_CM_CORE_REGADDR 159 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) DRA7XX_CM_CORE_REGADDR 165 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 167 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 169 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) DRA7XX_CM_CORE_REGADDR 171 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) DRA7XX_CM_CORE_REGADDR 173 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) DRA7XX_CM_CORE_REGADDR 175 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) DRA7XX_CM_CORE_REGADDR 177 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) DRA7XX_CM_CORE_REGADDR 179 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) DRA7XX_CM_CORE_REGADDR 181 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) DRA7XX_CM_CORE_REGADDR 183 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) DRA7XX_CM_CORE_REGADDR 185 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) DRA7XX_CM_CORE_REGADDR 187 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) DRA7XX_CM_CORE_REGADDR 189 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) DRA7XX_CM_CORE_REGADDR 191 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) DRA7XX_CM_CORE_REGADDR 193 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) DRA7XX_CM_CORE_REGADDR 195 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) DRA7XX_CM_CORE_REGADDR 197 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) DRA7XX_CM_CORE_REGADDR 199 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) DRA7XX_CM_CORE_REGADDR 201 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) DRA7XX_CM_CORE_REGADDR 203 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) DRA7XX_CM_CORE_REGADDR 205 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) DRA7XX_CM_CORE_REGADDR 207 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) DRA7XX_CM_CORE_REGADDR 209 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) DRA7XX_CM_CORE_REGADDR 214 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) DRA7XX_CM_CORE_REGADDR 219 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) DRA7XX_CM_CORE_REGADDR 222 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) DRA7XX_CM_CORE_REGADDR 224 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) DRA7XX_CM_CORE_REGADDR 226 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) DRA7XX_CM_CORE_REGADDR 228 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) DRA7XX_CM_CORE_REGADDR 230 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) DRA7XX_CM_CORE_REGADDR 232 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) DRA7XX_CM_CORE_REGADDR 237 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) DRA7XX_CM_CORE_REGADDR 239 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) DRA7XX_CM_CORE_REGADDR 241 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) DRA7XX_CM_CORE_REGADDR 243 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) DRA7XX_CM_CORE_REGADDR 245 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) DRA7XX_CM_CORE_REGADDR 247 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) DRA7XX_CM_CORE_REGADDR 249 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) DRA7XX_CM_CORE_REGADDR 251 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) DRA7XX_CM_CORE_REGADDR 253 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) DRA7XX_CM_CORE_REGADDR 255 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) DRA7XX_CM_CORE_REGADDR 257 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) DRA7XX_CM_CORE_REGADDR 259 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) DRA7XX_CM_CORE_REGADDR 261 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) DRA7XX_CM_CORE_REGADDR 263 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) DRA7XX_CM_CORE_REGADDR 265 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) DRA7XX_CM_CORE_REGADDR 267 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) DRA7XX_CM_CORE_REGADDR 269 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) DRA7XX_CM_CORE_REGADDR 271 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) DRA7XX_CM_CORE_REGADDR 273 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) DRA7XX_CM_CORE_REGADDR 275 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) DRA7XX_CM_CORE_REGADDR 277 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) DRA7XX_CM_CORE_REGADDR 280 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) DRA7XX_CM_CORE_REGADDR 282 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) DRA7XX_CM_CORE_REGADDR 284 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) DRA7XX_CM_CORE_REGADDR 286 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) DRA7XX_CM_CORE_REGADDR 288 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) DRA7XX_CM_CORE_REGADDR 295 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 297 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 303 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 305 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 307 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) DRA7XX_CM_CORE_REGADDR 309 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) DRA7XX_CM_CORE_REGADDR 311 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 313 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) DRA7XX_CM_CORE_REGADDR 320 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 322 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) DRA7XX_CM_CORE_REGADDR 324 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) DRA7XX_CM_CORE_REGADDR 331 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 338 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 340 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) DRA7XX_CM_CORE_REGADDR 342 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 344 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) DRA7XX_CM_CORE_REGADDR 346 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) DRA7XX_CM_CORE_REGADDR 348 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) DRA7XX_CM_CORE_REGADDR 350 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) DRA7XX_CM_CORE_REGADDR 352 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) DRA7XX_CM_CORE_REGADDR 356 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) DRA7XX_CM_CORE_REGADDR 358 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) DRA7XX_CM_CORE_REGADDR 363 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) DRA7XX_CM_CORE_REGADDR 365 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) DRA7XX_CM_CORE_REGADDR 367 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) DRA7XX_CM_CORE_REGADDR 369 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) DRA7XX_CM_CORE_REGADDR 374 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 380 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) DRA7XX_CM_CORE_REGADDR 382 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) DRA7XX_CM_CORE_REGADDR 384 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) DRA7XX_CM_CORE_REGADDR 386 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) DRA7XX_CM_CORE_REGADDR 388 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) DRA7XX_CM_CORE_REGADDR 390 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) DRA7XX_CM_CORE_REGADDR 392 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) DRA7XX_CM_CORE_REGADDR 394 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) DRA7XX_CM_CORE_REGADDR 396 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) DRA7XX_CM_CORE_REGADDR 398 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) DRA7XX_CM_CORE_REGADDR 400 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) DRA7XX_CM_CORE_REGADDR 402 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) DRA7XX_CM_CORE_REGADDR 404 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) DRA7XX_CM_CORE_REGADDR 406 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) DRA7XX_CM_CORE_REGADDR 408 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) DRA7XX_CM_CORE_REGADDR 410 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) DRA7XX_CM_CORE_REGADDR 412 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) DRA7XX_CM_CORE_REGADDR 414 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) DRA7XX_CM_CORE_REGADDR 416 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) DRA7XX_CM_CORE_REGADDR 418 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) DRA7XX_CM_CORE_REGADDR 420 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) DRA7XX_CM_CORE_REGADDR 422 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) DRA7XX_CM_CORE_REGADDR 424 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) DRA7XX_CM_CORE_REGADDR 426 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) DRA7XX_CM_CORE_REGADDR 428 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) DRA7XX_CM_CORE_REGADDR 430 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) DRA7XX_CM_CORE_REGADDR 432 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) DRA7XX_CM_CORE_REGADDR 434 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) DRA7XX_CM_CORE_REGADDR 436 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) DRA7XX_CM_CORE_REGADDR 438 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) DRA7XX_CM_CORE_REGADDR 440 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) DRA7XX_CM_CORE_REGADDR 442 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) DRA7XX_CM_CORE_REGADDR 444 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) DRA7XX_CM_CORE_REGADDR 446 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) DRA7XX_CM_CORE_REGADDR 448 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) DRA7XX_CM_CORE_REGADDR 450 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) DRA7XX_CM_CORE_REGADDR 452 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) DRA7XX_CM_CORE_REGADDR 454 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) DRA7XX_CM_CORE_REGADDR 456 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) DRA7XX_CM_CORE_REGADDR 458 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) DRA7XX_CM_CORE_REGADDR 460 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) DRA7XX_CM_CORE_REGADDR 462 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) DRA7XX_CM_CORE_REGADDR 464 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) DRA7XX_CM_CORE_REGADDR 466 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) DRA7XX_CM_CORE_REGADDR 468 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) DRA7XX_CM_CORE_REGADDR 470 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) DRA7XX_CM_CORE_REGADDR 475 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) DRA7XX_CM_CORE_REGADDR 477 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) DRA7XX_CM_CORE_REGADDR 479 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) DRA7XX_CM_CORE_REGADDR 481 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) DRA7XX_CM_CORE_REGADDR 483 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) DRA7XX_CM_CORE_REGADDR 485 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) DRA7XX_CM_CORE_REGADDR 487 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) DRA7XX_CM_CORE_REGADDR 489 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) DRA7XX_CM_CORE_REGADDR 491 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) DRA7XX_CM_CORE_REGADDR 493 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) DRA7XX_CM_CORE_REGADDR 495 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) DRA7XX_CM_CORE_REGADDR 497 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) DRA7XX_CM_CORE_REGADDR 499 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) DRA7XX_CM_CORE_REGADDR 501 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) DRA7XX_CM_CORE_REGADDR 505 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) DRA7XX_CM_CORE_REGADDR 507 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)