DRA7XX_CM_CORE_L4PER_INST 316 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L4PER_INST, DRA7XX_CM_CORE_L4PER_INST 326 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L4PER_INST, DRA7XX_CM_CORE_L4PER_INST 404 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L4PER_INST, DRA7XX_CM_CORE_L4PER_INST 616 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L4PER_INST, DRA7XX_CM_CORE_L4PER_INST 380 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) DRA7XX_CM_CORE_L4PER_INST 382 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) DRA7XX_CM_CORE_L4PER_INST 384 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) DRA7XX_CM_CORE_L4PER_INST 386 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) DRA7XX_CM_CORE_L4PER_INST 388 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) DRA7XX_CM_CORE_L4PER_INST 390 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) DRA7XX_CM_CORE_L4PER_INST 392 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) DRA7XX_CM_CORE_L4PER_INST 394 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) DRA7XX_CM_CORE_L4PER_INST 396 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) DRA7XX_CM_CORE_L4PER_INST 398 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) DRA7XX_CM_CORE_L4PER_INST 400 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) DRA7XX_CM_CORE_L4PER_INST 402 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) DRA7XX_CM_CORE_L4PER_INST 404 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) DRA7XX_CM_CORE_L4PER_INST 406 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) DRA7XX_CM_CORE_L4PER_INST 408 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) DRA7XX_CM_CORE_L4PER_INST 410 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) DRA7XX_CM_CORE_L4PER_INST 412 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) DRA7XX_CM_CORE_L4PER_INST 414 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) DRA7XX_CM_CORE_L4PER_INST 416 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) DRA7XX_CM_CORE_L4PER_INST 418 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) DRA7XX_CM_CORE_L4PER_INST 420 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) DRA7XX_CM_CORE_L4PER_INST 422 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) DRA7XX_CM_CORE_L4PER_INST 424 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) DRA7XX_CM_CORE_L4PER_INST 426 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) DRA7XX_CM_CORE_L4PER_INST 428 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) DRA7XX_CM_CORE_L4PER_INST 430 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) DRA7XX_CM_CORE_L4PER_INST 432 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) DRA7XX_CM_CORE_L4PER_INST 434 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) DRA7XX_CM_CORE_L4PER_INST 436 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) DRA7XX_CM_CORE_L4PER_INST 438 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) DRA7XX_CM_CORE_L4PER_INST 440 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) DRA7XX_CM_CORE_L4PER_INST 442 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) DRA7XX_CM_CORE_L4PER_INST 444 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) DRA7XX_CM_CORE_L4PER_INST 446 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) DRA7XX_CM_CORE_L4PER_INST 448 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) DRA7XX_CM_CORE_L4PER_INST 450 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) DRA7XX_CM_CORE_L4PER_INST 452 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) DRA7XX_CM_CORE_L4PER_INST 454 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) DRA7XX_CM_CORE_L4PER_INST 456 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) DRA7XX_CM_CORE_L4PER_INST 458 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) DRA7XX_CM_CORE_L4PER_INST 460 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) DRA7XX_CM_CORE_L4PER_INST 462 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) DRA7XX_CM_CORE_L4PER_INST 464 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) DRA7XX_CM_CORE_L4PER_INST 466 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) DRA7XX_CM_CORE_L4PER_INST 468 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) DRA7XX_CM_CORE_L4PER_INST 470 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) DRA7XX_CM_CORE_L4PER_INST 475 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) DRA7XX_CM_CORE_L4PER_INST 477 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) DRA7XX_CM_CORE_L4PER_INST 479 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) DRA7XX_CM_CORE_L4PER_INST 481 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) DRA7XX_CM_CORE_L4PER_INST 483 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) DRA7XX_CM_CORE_L4PER_INST 485 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) DRA7XX_CM_CORE_L4PER_INST 487 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) DRA7XX_CM_CORE_L4PER_INST 489 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) DRA7XX_CM_CORE_L4PER_INST 491 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) DRA7XX_CM_CORE_L4PER_INST 493 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) DRA7XX_CM_CORE_L4PER_INST 495 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) DRA7XX_CM_CORE_L4PER_INST 497 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) DRA7XX_CM_CORE_L4PER_INST 499 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) DRA7XX_CM_CORE_L4PER_INST 501 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) DRA7XX_CM_CORE_L4PER_INST 505 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) DRA7XX_CM_CORE_L4PER_INST 507 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)