DRA7XX_CM_CORE_L3INIT_INST 392 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, DRA7XX_CM_CORE_L3INIT_INST 477 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, DRA7XX_CM_CORE_L3INIT_INST 519 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, DRA7XX_CM_CORE_L3INIT_INST 338 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) DRA7XX_CM_CORE_L3INIT_INST 340 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) DRA7XX_CM_CORE_L3INIT_INST 342 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) DRA7XX_CM_CORE_L3INIT_INST 344 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) DRA7XX_CM_CORE_L3INIT_INST 346 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) DRA7XX_CM_CORE_L3INIT_INST 348 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) DRA7XX_CM_CORE_L3INIT_INST 350 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) DRA7XX_CM_CORE_L3INIT_INST 352 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) DRA7XX_CM_CORE_L3INIT_INST 356 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) DRA7XX_CM_CORE_L3INIT_INST 358 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) DRA7XX_CM_CORE_L3INIT_INST 363 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) DRA7XX_CM_CORE_L3INIT_INST 365 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) DRA7XX_CM_CORE_L3INIT_INST 367 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) DRA7XX_CM_CORE_L3INIT_INST 369 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)