DRA7XX_CM_CORE_CORE_INST 380 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 416 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 489 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 499 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 531 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 541 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 561 arch/arm/mach-omap2/clockdomains7xx_data.c .cm_inst = DRA7XX_CM_CORE_CORE_INST, DRA7XX_CM_CORE_CORE_INST 165 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) DRA7XX_CM_CORE_CORE_INST 167 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) DRA7XX_CM_CORE_CORE_INST 169 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) DRA7XX_CM_CORE_CORE_INST 171 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) DRA7XX_CM_CORE_CORE_INST 173 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) DRA7XX_CM_CORE_CORE_INST 175 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) DRA7XX_CM_CORE_CORE_INST 177 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) DRA7XX_CM_CORE_CORE_INST 179 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) DRA7XX_CM_CORE_CORE_INST 181 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) DRA7XX_CM_CORE_CORE_INST 183 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) DRA7XX_CM_CORE_CORE_INST 185 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) DRA7XX_CM_CORE_CORE_INST 187 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) DRA7XX_CM_CORE_CORE_INST 189 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) DRA7XX_CM_CORE_CORE_INST 191 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) DRA7XX_CM_CORE_CORE_INST 193 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) DRA7XX_CM_CORE_CORE_INST 195 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) DRA7XX_CM_CORE_CORE_INST 197 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) DRA7XX_CM_CORE_CORE_INST 199 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) DRA7XX_CM_CORE_CORE_INST 201 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) DRA7XX_CM_CORE_CORE_INST 203 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) DRA7XX_CM_CORE_CORE_INST 205 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) DRA7XX_CM_CORE_CORE_INST 207 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) DRA7XX_CM_CORE_CORE_INST 209 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) DRA7XX_CM_CORE_CORE_INST 214 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) DRA7XX_CM_CORE_CORE_INST 219 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) DRA7XX_CM_CORE_CORE_INST 222 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) DRA7XX_CM_CORE_CORE_INST 224 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) DRA7XX_CM_CORE_CORE_INST 226 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) DRA7XX_CM_CORE_CORE_INST 228 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) DRA7XX_CM_CORE_CORE_INST 230 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) DRA7XX_CM_CORE_CORE_INST 232 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) DRA7XX_CM_CORE_CORE_INST 237 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) DRA7XX_CM_CORE_CORE_INST 239 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) DRA7XX_CM_CORE_CORE_INST 241 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) DRA7XX_CM_CORE_CORE_INST 243 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) DRA7XX_CM_CORE_CORE_INST 245 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) DRA7XX_CM_CORE_CORE_INST 247 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) DRA7XX_CM_CORE_CORE_INST 249 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) DRA7XX_CM_CORE_CORE_INST 251 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) DRA7XX_CM_CORE_CORE_INST 253 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) DRA7XX_CM_CORE_CORE_INST 255 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) DRA7XX_CM_CORE_CORE_INST 257 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) DRA7XX_CM_CORE_CORE_INST 259 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) DRA7XX_CM_CORE_CORE_INST 261 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) DRA7XX_CM_CORE_CORE_INST 263 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) DRA7XX_CM_CORE_CORE_INST 265 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) DRA7XX_CM_CORE_CORE_INST 267 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) DRA7XX_CM_CORE_CORE_INST 269 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) DRA7XX_CM_CORE_CORE_INST 271 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) DRA7XX_CM_CORE_CORE_INST 273 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) DRA7XX_CM_CORE_CORE_INST 275 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) DRA7XX_CM_CORE_CORE_INST 277 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) DRA7XX_CM_CORE_CORE_INST 280 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) DRA7XX_CM_CORE_CORE_INST 282 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) DRA7XX_CM_CORE_CORE_INST 284 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) DRA7XX_CM_CORE_CORE_INST 286 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) DRA7XX_CM_CORE_CORE_INST 288 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)