DRA7XX_CM_CORE_CKGEN_INST 74 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) DRA7XX_CM_CORE_CKGEN_INST 76 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) DRA7XX_CM_CORE_CKGEN_INST 78 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) DRA7XX_CM_CORE_CKGEN_INST 80 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) DRA7XX_CM_CORE_CKGEN_INST 82 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) DRA7XX_CM_CORE_CKGEN_INST 84 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) DRA7XX_CM_CORE_CKGEN_INST 86 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) DRA7XX_CM_CORE_CKGEN_INST 88 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) DRA7XX_CM_CORE_CKGEN_INST 90 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) DRA7XX_CM_CORE_CKGEN_INST 92 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) DRA7XX_CM_CORE_CKGEN_INST 94 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) DRA7XX_CM_CORE_CKGEN_INST 98 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) DRA7XX_CM_CORE_CKGEN_INST 100 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) DRA7XX_CM_CORE_CKGEN_INST 102 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) DRA7XX_CM_CORE_CKGEN_INST 104 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) DRA7XX_CM_CORE_CKGEN_INST 106 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) DRA7XX_CM_CORE_CKGEN_INST 110 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) DRA7XX_CM_CORE_CKGEN_INST 112 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) DRA7XX_CM_CORE_CKGEN_INST 114 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) DRA7XX_CM_CORE_CKGEN_INST 116 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) DRA7XX_CM_CORE_CKGEN_INST 118 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) DRA7XX_CM_CORE_CKGEN_INST 120 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) DRA7XX_CM_CORE_CKGEN_INST 124 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) DRA7XX_CM_CORE_CKGEN_INST 126 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) DRA7XX_CM_CORE_CKGEN_INST 128 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) DRA7XX_CM_CORE_CKGEN_INST 130 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)