DRA7XX_CM_CORE_AON_REGADDR 62 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) DRA7XX_CM_CORE_AON_REGADDR 71 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) DRA7XX_CM_CORE_AON_REGADDR 73 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) DRA7XX_CM_CORE_AON_REGADDR 76 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 78 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) DRA7XX_CM_CORE_AON_REGADDR 80 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) DRA7XX_CM_CORE_AON_REGADDR 82 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) DRA7XX_CM_CORE_AON_REGADDR 84 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) DRA7XX_CM_CORE_AON_REGADDR 86 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) DRA7XX_CM_CORE_AON_REGADDR 88 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) DRA7XX_CM_CORE_AON_REGADDR 90 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) DRA7XX_CM_CORE_AON_REGADDR 92 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) DRA7XX_CM_CORE_AON_REGADDR 94 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) DRA7XX_CM_CORE_AON_REGADDR 98 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) DRA7XX_CM_CORE_AON_REGADDR 100 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) DRA7XX_CM_CORE_AON_REGADDR 102 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) DRA7XX_CM_CORE_AON_REGADDR 104 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) DRA7XX_CM_CORE_AON_REGADDR 106 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) DRA7XX_CM_CORE_AON_REGADDR 108 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) DRA7XX_CM_CORE_AON_REGADDR 110 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) DRA7XX_CM_CORE_AON_REGADDR 112 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) DRA7XX_CM_CORE_AON_REGADDR 114 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) DRA7XX_CM_CORE_AON_REGADDR 118 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) DRA7XX_CM_CORE_AON_REGADDR 120 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) DRA7XX_CM_CORE_AON_REGADDR 122 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) DRA7XX_CM_CORE_AON_REGADDR 124 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) DRA7XX_CM_CORE_AON_REGADDR 126 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) DRA7XX_CM_CORE_AON_REGADDR 128 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) DRA7XX_CM_CORE_AON_REGADDR 130 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) DRA7XX_CM_CORE_AON_REGADDR 134 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) DRA7XX_CM_CORE_AON_REGADDR 136 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) DRA7XX_CM_CORE_AON_REGADDR 138 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) DRA7XX_CM_CORE_AON_REGADDR 140 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) DRA7XX_CM_CORE_AON_REGADDR 142 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) DRA7XX_CM_CORE_AON_REGADDR 144 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) DRA7XX_CM_CORE_AON_REGADDR 146 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) DRA7XX_CM_CORE_AON_REGADDR 150 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) DRA7XX_CM_CORE_AON_REGADDR 152 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) DRA7XX_CM_CORE_AON_REGADDR 154 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) DRA7XX_CM_CORE_AON_REGADDR 156 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) DRA7XX_CM_CORE_AON_REGADDR 158 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) DRA7XX_CM_CORE_AON_REGADDR 160 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) DRA7XX_CM_CORE_AON_REGADDR 162 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) DRA7XX_CM_CORE_AON_REGADDR 166 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) DRA7XX_CM_CORE_AON_REGADDR 168 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) DRA7XX_CM_CORE_AON_REGADDR 170 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) DRA7XX_CM_CORE_AON_REGADDR 172 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) DRA7XX_CM_CORE_AON_REGADDR 174 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) DRA7XX_CM_CORE_AON_REGADDR 176 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) DRA7XX_CM_CORE_AON_REGADDR 180 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) DRA7XX_CM_CORE_AON_REGADDR 186 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) DRA7XX_CM_CORE_AON_REGADDR 188 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) DRA7XX_CM_CORE_AON_REGADDR 190 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) DRA7XX_CM_CORE_AON_REGADDR 192 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) DRA7XX_CM_CORE_AON_REGADDR 194 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) DRA7XX_CM_CORE_AON_REGADDR 196 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) DRA7XX_CM_CORE_AON_REGADDR 200 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) DRA7XX_CM_CORE_AON_REGADDR 202 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) DRA7XX_CM_CORE_AON_REGADDR 204 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) DRA7XX_CM_CORE_AON_REGADDR 206 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) DRA7XX_CM_CORE_AON_REGADDR 208 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) DRA7XX_CM_CORE_AON_REGADDR 210 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) DRA7XX_CM_CORE_AON_REGADDR 212 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) DRA7XX_CM_CORE_AON_REGADDR 214 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) DRA7XX_CM_CORE_AON_REGADDR 216 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) DRA7XX_CM_CORE_AON_REGADDR 218 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) DRA7XX_CM_CORE_AON_REGADDR 220 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) DRA7XX_CM_CORE_AON_REGADDR 224 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) DRA7XX_CM_CORE_AON_REGADDR 226 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) DRA7XX_CM_CORE_AON_REGADDR 228 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) DRA7XX_CM_CORE_AON_REGADDR 230 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) DRA7XX_CM_CORE_AON_REGADDR 232 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) DRA7XX_CM_CORE_AON_REGADDR 234 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec) DRA7XX_CM_CORE_AON_REGADDR 243 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 245 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028) DRA7XX_CM_CORE_AON_REGADDR 252 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 259 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 262 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050) DRA7XX_CM_CORE_AON_REGADDR 264 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058) DRA7XX_CM_CORE_AON_REGADDR 266 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060) DRA7XX_CM_CORE_AON_REGADDR 268 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068) DRA7XX_CM_CORE_AON_REGADDR 270 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070) DRA7XX_CM_CORE_AON_REGADDR 272 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078) DRA7XX_CM_CORE_AON_REGADDR 274 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080) DRA7XX_CM_CORE_AON_REGADDR 281 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 287 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 293 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 299 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 305 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020) DRA7XX_CM_CORE_AON_REGADDR 310 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004) DRA7XX_CM_CORE_AON_REGADDR 315 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)