DRA7XX_CM_CORE_AON_IPU_INST  368 arch/arm/mach-omap2/clockdomains7xx_data.c 	.cm_inst	  = DRA7XX_CM_CORE_AON_IPU_INST,
DRA7XX_CM_CORE_AON_IPU_INST  458 arch/arm/mach-omap2/clockdomains7xx_data.c 	.cm_inst	  = DRA7XX_CM_CORE_AON_IPU_INST,
DRA7XX_CM_CORE_AON_IPU_INST  259 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU1_IPU1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
DRA7XX_CM_CORE_AON_IPU_INST  262 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_MCASP1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
DRA7XX_CM_CORE_AON_IPU_INST  264 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
DRA7XX_CM_CORE_AON_IPU_INST  266 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
DRA7XX_CM_CORE_AON_IPU_INST  268 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER7_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
DRA7XX_CM_CORE_AON_IPU_INST  270 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_TIMER8_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
DRA7XX_CM_CORE_AON_IPU_INST  272 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_I2C5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
DRA7XX_CM_CORE_AON_IPU_INST  274 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IPU_UART6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)