DRA7XX_CM_CORE_AON_CKGEN_INST 71 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) DRA7XX_CM_CORE_AON_CKGEN_INST 73 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) DRA7XX_CM_CORE_AON_CKGEN_INST 76 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) DRA7XX_CM_CORE_AON_CKGEN_INST 78 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) DRA7XX_CM_CORE_AON_CKGEN_INST 80 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) DRA7XX_CM_CORE_AON_CKGEN_INST 82 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) DRA7XX_CM_CORE_AON_CKGEN_INST 84 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) DRA7XX_CM_CORE_AON_CKGEN_INST 86 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) DRA7XX_CM_CORE_AON_CKGEN_INST 88 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) DRA7XX_CM_CORE_AON_CKGEN_INST 90 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) DRA7XX_CM_CORE_AON_CKGEN_INST 92 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) DRA7XX_CM_CORE_AON_CKGEN_INST 94 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) DRA7XX_CM_CORE_AON_CKGEN_INST 98 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) DRA7XX_CM_CORE_AON_CKGEN_INST 100 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) DRA7XX_CM_CORE_AON_CKGEN_INST 102 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) DRA7XX_CM_CORE_AON_CKGEN_INST 104 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) DRA7XX_CM_CORE_AON_CKGEN_INST 106 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) DRA7XX_CM_CORE_AON_CKGEN_INST 108 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) DRA7XX_CM_CORE_AON_CKGEN_INST 110 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) DRA7XX_CM_CORE_AON_CKGEN_INST 112 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) DRA7XX_CM_CORE_AON_CKGEN_INST 114 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) DRA7XX_CM_CORE_AON_CKGEN_INST 118 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) DRA7XX_CM_CORE_AON_CKGEN_INST 120 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) DRA7XX_CM_CORE_AON_CKGEN_INST 122 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) DRA7XX_CM_CORE_AON_CKGEN_INST 124 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) DRA7XX_CM_CORE_AON_CKGEN_INST 126 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) DRA7XX_CM_CORE_AON_CKGEN_INST 128 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) DRA7XX_CM_CORE_AON_CKGEN_INST 130 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) DRA7XX_CM_CORE_AON_CKGEN_INST 134 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) DRA7XX_CM_CORE_AON_CKGEN_INST 136 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) DRA7XX_CM_CORE_AON_CKGEN_INST 138 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) DRA7XX_CM_CORE_AON_CKGEN_INST 140 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) DRA7XX_CM_CORE_AON_CKGEN_INST 142 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) DRA7XX_CM_CORE_AON_CKGEN_INST 144 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) DRA7XX_CM_CORE_AON_CKGEN_INST 146 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) DRA7XX_CM_CORE_AON_CKGEN_INST 150 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) DRA7XX_CM_CORE_AON_CKGEN_INST 152 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) DRA7XX_CM_CORE_AON_CKGEN_INST 154 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) DRA7XX_CM_CORE_AON_CKGEN_INST 156 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) DRA7XX_CM_CORE_AON_CKGEN_INST 158 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) DRA7XX_CM_CORE_AON_CKGEN_INST 160 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) DRA7XX_CM_CORE_AON_CKGEN_INST 162 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) DRA7XX_CM_CORE_AON_CKGEN_INST 166 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) DRA7XX_CM_CORE_AON_CKGEN_INST 168 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) DRA7XX_CM_CORE_AON_CKGEN_INST 170 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) DRA7XX_CM_CORE_AON_CKGEN_INST 172 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) DRA7XX_CM_CORE_AON_CKGEN_INST 174 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) DRA7XX_CM_CORE_AON_CKGEN_INST 176 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) DRA7XX_CM_CORE_AON_CKGEN_INST 180 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) DRA7XX_CM_CORE_AON_CKGEN_INST 186 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) DRA7XX_CM_CORE_AON_CKGEN_INST 188 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) DRA7XX_CM_CORE_AON_CKGEN_INST 190 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) DRA7XX_CM_CORE_AON_CKGEN_INST 192 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) DRA7XX_CM_CORE_AON_CKGEN_INST 194 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) DRA7XX_CM_CORE_AON_CKGEN_INST 196 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) DRA7XX_CM_CORE_AON_CKGEN_INST 200 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) DRA7XX_CM_CORE_AON_CKGEN_INST 202 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) DRA7XX_CM_CORE_AON_CKGEN_INST 204 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) DRA7XX_CM_CORE_AON_CKGEN_INST 206 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) DRA7XX_CM_CORE_AON_CKGEN_INST 208 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) DRA7XX_CM_CORE_AON_CKGEN_INST 210 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) DRA7XX_CM_CORE_AON_CKGEN_INST 212 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) DRA7XX_CM_CORE_AON_CKGEN_INST 214 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) DRA7XX_CM_CORE_AON_CKGEN_INST 216 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) DRA7XX_CM_CORE_AON_CKGEN_INST 218 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) DRA7XX_CM_CORE_AON_CKGEN_INST 220 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) DRA7XX_CM_CORE_AON_CKGEN_INST 224 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) DRA7XX_CM_CORE_AON_CKGEN_INST 226 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) DRA7XX_CM_CORE_AON_CKGEN_INST 228 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) DRA7XX_CM_CORE_AON_CKGEN_INST 230 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) DRA7XX_CM_CORE_AON_CKGEN_INST 232 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) DRA7XX_CM_CORE_AON_CKGEN_INST 234 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)