DP_VID_N_MUL      333 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		if (enc110->se_mask->DP_VID_N_MUL)
DP_VID_N_MUL      334 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
DP_VID_N_MUL      369 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
DP_VID_N_MUL      497 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t DP_VID_N_MUL;
DP_VID_N_MUL      628 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_VID_N_MUL;
DP_VID_N_MUL      970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 				DP_VID_N_MUL, n_multiply);
DP_VID_N_MUL      302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
DP_VID_N_MUL      464 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type DP_VID_N_MUL;\
DP_VID_N_MUL      492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 				DP_VID_N_MUL, n_multiply);