DP_TP_STATUS     1148 drivers/gpu/drm/i915/display/intel_ddi.c 		temp = I915_READ(DP_TP_STATUS(PORT_E));
DP_TP_STATUS     3146 drivers/gpu/drm/i915/display/intel_ddi.c 	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
DP_TP_STATUS     4057 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
DP_TP_STATUS      329 drivers/gpu/drm/i915/display/intel_dp_mst.c 	temp = I915_READ(DP_TP_STATUS(port));
DP_TP_STATUS      330 drivers/gpu/drm/i915/display/intel_dp_mst.c 	I915_WRITE(DP_TP_STATUS(port), temp);
DP_TP_STATUS      349 drivers/gpu/drm/i915/display/intel_dp_mst.c 	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
DP_TP_STATUS      546 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
DP_TP_STATUS      679 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
DP_TP_STATUS      699 drivers/gpu/drm/i915/gvt/handlers.c 		status_reg = DP_TP_STATUS(index);
DP_TP_STATUS     2459 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
DP_TP_STATUS     2460 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
DP_TP_STATUS     2461 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
DP_TP_STATUS     2462 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
DP_TP_STATUS     2463 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);