DP_TP_CTL 1110 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(PORT_E), DP_TP_CTL 1173 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(DP_TP_CTL(PORT_E)); DP_TP_CTL 1176 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(PORT_E), temp); DP_TP_CTL 1177 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(DP_TP_CTL(PORT_E)); DP_TP_CTL 1190 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(PORT_E), DP_TP_CTL 3142 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 3144 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 3161 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 3163 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 3164 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(DP_TP_CTL(port)); DP_TP_CTL 3337 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 3340 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 3768 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { DP_TP_CTL 3776 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 3779 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 3780 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(DP_TP_CTL(port)); DP_TP_CTL 3795 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 3796 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(DP_TP_CTL(port)); DP_TP_CTL 3318 drivers/gpu/drm/i915/display/intel_dp.c u32 temp = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 3344 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(DP_TP_CTL(port), temp); DP_TP_CTL 4042 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(DP_TP_CTL(port)); DP_TP_CTL 4045 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(DP_TP_CTL(port), val); DP_TP_CTL 566 drivers/gpu/drm/i915/gvt/handlers.c u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); DP_TP_CTL 685 drivers/gpu/drm/i915/gvt/handlers.c calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) DP_TP_CTL 2453 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); DP_TP_CTL 2454 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); DP_TP_CTL 2455 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); DP_TP_CTL 2456 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); DP_TP_CTL 2457 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);