DP_RECEIVER_CAP_SIZE  471 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE   41 drivers/gpu/drm/amd/amdgpu/atombios_dp.c #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
DP_RECEIVER_CAP_SIZE  485 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE  745 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE   77 drivers/gpu/drm/bridge/analogix-anx78xx.c 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE  783 drivers/gpu/drm/bridge/analogix-anx78xx.c 			       &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE  123 drivers/gpu/drm/drm_dp_helper.c void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
DP_RECEIVER_CAP_SIZE  138 drivers/gpu/drm/drm_dp_helper.c void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
DP_RECEIVER_CAP_SIZE  477 drivers/gpu/drm/drm_dp_helper.c int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE  508 drivers/gpu/drm/drm_dp_helper.c int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE  565 drivers/gpu/drm/drm_dp_helper.c 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE 2710 drivers/gpu/drm/drm_dp_mst_topology.c 		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE 2711 drivers/gpu/drm/drm_dp_mst_topology.c 		if (ret != DP_RECEIVER_CAP_SIZE) {
DP_RECEIVER_CAP_SIZE 2815 drivers/gpu/drm/drm_dp_mst_topology.c 		sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE 2816 drivers/gpu/drm/drm_dp_mst_topology.c 		if (sret != DP_RECEIVER_CAP_SIZE) {
DP_RECEIVER_CAP_SIZE 3706 drivers/gpu/drm/drm_dp_mst_topology.c 		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE 3707 drivers/gpu/drm/drm_dp_mst_topology.c 		seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf);
DP_RECEIVER_CAP_SIZE 1157 drivers/gpu/drm/i915/display/intel_display_types.h 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE 4399 drivers/gpu/drm/i915/i915_debugfs.c 	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
DP_RECEIVER_CAP_SIZE   96 drivers/gpu/drm/msm/edp/edp_ctrl.c 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE 1189 drivers/gpu/drm/msm/edp/edp_ctrl.c 				DP_RECEIVER_CAP_SIZE) < DP_RECEIVER_CAP_SIZE) {
DP_RECEIVER_CAP_SIZE 1191 drivers/gpu/drm/msm/edp/edp_ctrl.c 		memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE   37 drivers/gpu/drm/radeon/atombios_dp.c #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
DP_RECEIVER_CAP_SIZE  547 drivers/gpu/drm/radeon/atombios_dp.c 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE  844 drivers/gpu/drm/radeon/atombios_dp.c 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE  490 drivers/gpu/drm/radeon/radeon_mode.h 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE  369 drivers/gpu/drm/rockchip/cdn-dp-core.c 			       DP_RECEIVER_CAP_SIZE);
DP_RECEIVER_CAP_SIZE  101 drivers/gpu/drm/rockchip/cdn-dp-core.h 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
DP_RECEIVER_CAP_SIZE 1059 include/drm/drm_dp_helper.h void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
DP_RECEIVER_CAP_SIZE 1060 include/drm/drm_dp_helper.h void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
DP_RECEIVER_CAP_SIZE 1128 include/drm/drm_dp_helper.h drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1134 include/drm/drm_dp_helper.h drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1140 include/drm/drm_dp_helper.h drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1147 include/drm/drm_dp_helper.h drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1154 include/drm/drm_dp_helper.h drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1161 include/drm/drm_dp_helper.h drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1168 include/drm/drm_dp_helper.h drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_RECEIVER_CAP_SIZE 1372 include/drm/drm_dp_helper.h int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE 1374 include/drm/drm_dp_helper.h int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE 1377 include/drm/drm_dp_helper.h void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
DP_RECEIVER_CAP_SIZE  514 include/drm/drm_dp_mst_helper.h 	u8 dpcd[DP_RECEIVER_CAP_SIZE];