DP_PORT_EN       1089 drivers/gpu/drm/gma500/cdv_intel_dp.c 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
DP_PORT_EN       1193 drivers/gpu/drm/gma500/cdv_intel_dp.c 		if (!(dp_reg & DP_PORT_EN)) {
DP_PORT_EN       1510 drivers/gpu/drm/gma500/cdv_intel_dp.c 	DP |= DP_PORT_EN;
DP_PORT_EN       1685 drivers/gpu/drm/gma500/cdv_intel_dp.c 	if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
DP_PORT_EN       1699 drivers/gpu/drm/gma500/cdv_intel_dp.c 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
DP_PORT_EN       16904 drivers/gpu/drm/i915/display/intel_display.c 	if (val & DP_PORT_EN ||
DP_PORT_EN        734 drivers/gpu/drm/i915/display/intel_dp.c 	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
DP_PORT_EN        782 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
DP_PORT_EN        785 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
DP_PORT_EN       2926 drivers/gpu/drm/i915/display/intel_dp.c 	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
DP_PORT_EN       3106 drivers/gpu/drm/i915/display/intel_dp.c 	ret = val & DP_PORT_EN;
DP_PORT_EN       3402 drivers/gpu/drm/i915/display/intel_dp.c 	intel_dp->DP |= DP_PORT_EN;
DP_PORT_EN       3421 drivers/gpu/drm/i915/display/intel_dp.c 	if (WARN_ON(dp_reg & DP_PORT_EN))
DP_PORT_EN       4072 drivers/gpu/drm/i915/display/intel_dp.c 	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
DP_PORT_EN       4088 drivers/gpu/drm/i915/display/intel_dp.c 	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
DP_PORT_EN       4107 drivers/gpu/drm/i915/display/intel_dp.c 		DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
DP_PORT_EN       4112 drivers/gpu/drm/i915/display/intel_dp.c 		DP &= ~DP_PORT_EN;
DP_PORT_EN        166 drivers/gpu/drm/i915/display/intel_dp_link_training.c 	intel_dp->DP |= DP_PORT_EN;