DP_DPCD_REV       343 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 	ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
DP_DPCD_REV       500 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
DP_DPCD_REV      2483 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
DP_DPCD_REV      2675 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			core_link_read_dpcd(link, DP_DPCD_REV,
DP_DPCD_REV      2678 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				DP_DPCD_REV -
DP_DPCD_REV      2679 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				DP_DPCD_REV];
DP_DPCD_REV      2684 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				 DP_DPCD_REV];
DP_DPCD_REV      2710 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
DP_DPCD_REV      2746 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				DP_DPCD_REV,
DP_DPCD_REV      2788 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
DP_DPCD_REV      2818 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
DP_DPCD_REV      2822 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				 DP_DPCD_REV];
DP_DPCD_REV      2831 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				 DP_DPCD_REV];
DP_DPCD_REV      2837 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		DP_MAX_LANE_COUNT - DP_DPCD_REV];
DP_DPCD_REV      2840 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
DP_DPCD_REV      2845 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		DP_MAX_LINK_RATE - DP_DPCD_REV];
DP_DPCD_REV      2851 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
DP_DPCD_REV       782 drivers/gpu/drm/bridge/analogix-anx78xx.c 	err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
DP_DPCD_REV       131 drivers/gpu/drm/drm_dp_helper.c 	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
DP_DPCD_REV       283 drivers/gpu/drm/drm_dp_helper.c 	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
DP_DPCD_REV       357 drivers/gpu/drm/drm_dp_helper.c 	err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
DP_DPCD_REV      2710 drivers/gpu/drm/drm_dp_mst_topology.c 		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
DP_DPCD_REV      2815 drivers/gpu/drm/drm_dp_mst_topology.c 		sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
DP_DPCD_REV      3706 drivers/gpu/drm/drm_dp_mst_topology.c 		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE);
DP_DPCD_REV       329 drivers/gpu/drm/gma500/cdv_intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
DP_DPCD_REV      1079 drivers/gpu/drm/gma500/cdv_intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
DP_DPCD_REV      1115 drivers/gpu/drm/gma500/cdv_intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
DP_DPCD_REV      1712 drivers/gpu/drm/gma500/cdv_intel_dp.c 		if (intel_dp->dpcd[DP_DPCD_REV] != 0)
DP_DPCD_REV      2119 drivers/gpu/drm/gma500/cdv_intel_dp.c 		ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV,
DP_DPCD_REV      3015 drivers/gpu/drm/i915/display/intel_dp.c 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
DP_DPCD_REV      3042 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
DP_DPCD_REV      4155 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
DP_DPCD_REV      4180 drivers/gpu/drm/i915/display/intel_dp.c 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
DP_DPCD_REV      4205 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
DP_DPCD_REV      4234 drivers/gpu/drm/i915/display/intel_dp.c 	WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
DP_DPCD_REV      4359 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
DP_DPCD_REV      4375 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
DP_DPCD_REV      4912 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
DP_DPCD_REV      5012 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
DP_DPCD_REV      5027 drivers/gpu/drm/i915/display/intel_dp.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
DP_DPCD_REV       184 drivers/gpu/drm/i915/display/intel_dp_link_training.c 	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
DP_DPCD_REV       175 drivers/gpu/drm/i915/display/intel_lspcon.c 	if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
DP_DPCD_REV      2512 drivers/gpu/drm/i915/i915_debugfs.c 	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
DP_DPCD_REV      4399 drivers/gpu/drm/i915/i915_debugfs.c 	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
DP_DPCD_REV      1188 drivers/gpu/drm/msm/edp/edp_ctrl.c 	if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd,
DP_DPCD_REV      1379 drivers/gpu/drm/nouveau/dispnv50/disp.c 	ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
DP_DPCD_REV        71 drivers/gpu/drm/nouveau/nouveau_dp.c 	ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
DP_DPCD_REV       392 drivers/gpu/drm/radeon/atombios_dp.c 	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
DP_DPCD_REV       678 drivers/gpu/drm/radeon/radeon_dp_mst.c 	if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
DP_DPCD_REV       368 drivers/gpu/drm/rockchip/cdn-dp-core.c 	ret = cdn_dp_dpcd_read(dp, DP_DPCD_REV, dp->dpcd,
DP_DPCD_REV      1142 include/drm/drm_dp_helper.h 	return dpcd[DP_DPCD_REV] >= 0x11 &&
DP_DPCD_REV      1149 include/drm/drm_dp_helper.h 	return dpcd[DP_DPCD_REV] >= 0x12 &&
DP_DPCD_REV      1156 include/drm/drm_dp_helper.h 	return dpcd[DP_DPCD_REV] >= 0x14 &&
DP_DPCD_REV      1163 include/drm/drm_dp_helper.h 	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :