DP_A             1206 drivers/gpu/drm/i915/display/intel_display.c 			intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
DP_A             15248 drivers/gpu/drm/i915/display/intel_display.c 	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
DP_A             15412 drivers/gpu/drm/i915/display/intel_display.c 			intel_dp_init(dev_priv, DP_A, PORT_A);
DP_A             2937 drivers/gpu/drm/i915/display/intel_dp.c 	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
DP_A             2966 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(DP_A, intel_dp->DP);
DP_A             2967 drivers/gpu/drm/i915/display/intel_dp.c 	POSTING_READ(DP_A);
DP_A             2981 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(DP_A, intel_dp->DP);
DP_A             2982 drivers/gpu/drm/i915/display/intel_dp.c 	POSTING_READ(DP_A);
DP_A             3000 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(DP_A, intel_dp->DP);
DP_A             3001 drivers/gpu/drm/i915/display/intel_dp.c 	POSTING_READ(DP_A);
DP_A             3195 drivers/gpu/drm/i915/display/intel_dp.c 		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)