DPU_REG_WRITE 78 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); DPU_REG_WRITE 85 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); DPU_REG_WRITE 112 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); DPU_REG_WRITE 252 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); DPU_REG_WRITE 284 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0); DPU_REG_WRITE 285 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0); DPU_REG_WRITE 286 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0); DPU_REG_WRITE 287 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0); DPU_REG_WRITE 419 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); DPU_REG_WRITE 420 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); DPU_REG_WRITE 421 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); DPU_REG_WRITE 422 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); DPU_REG_WRITE 452 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(c, CTL_TOP, intf_cfg); DPU_REG_WRITE 871 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); DPU_REG_WRITE 873 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); DPU_REG_WRITE 916 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); DPU_REG_WRITE 918 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); DPU_REG_WRITE 959 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 0xffffffff); DPU_REG_WRITE 975 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000); DPU_REG_WRITE 1003 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, DPU_REG_WRITE 1025 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_REG_WRITE 1054 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_REG_WRITE 169 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); DPU_REG_WRITE 170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); DPU_REG_WRITE 171 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, DPU_REG_WRITE 173 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); DPU_REG_WRITE 174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); DPU_REG_WRITE 175 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); DPU_REG_WRITE 176 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); DPU_REG_WRITE 177 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); DPU_REG_WRITE 178 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); DPU_REG_WRITE 179 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); DPU_REG_WRITE 180 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); DPU_REG_WRITE 181 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); DPU_REG_WRITE 182 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); DPU_REG_WRITE 183 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE 184 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE 185 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); DPU_REG_WRITE 194 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); DPU_REG_WRITE 212 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_PROG_FETCH_START, DPU_REG_WRITE 218 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); DPU_REG_WRITE 73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); DPU_REG_WRITE 80 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_OP_MODE, op_mode); DPU_REG_WRITE 90 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BORDER_COLOR_0, DPU_REG_WRITE 93 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BORDER_COLOR_1, DPU_REG_WRITE 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); DPU_REG_WRITE 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); DPU_REG_WRITE 131 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); DPU_REG_WRITE 132 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); DPU_REG_WRITE 133 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); DPU_REG_WRITE 147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c DPU_REG_WRITE(c, LM_OP_MODE, op_mode); DPU_REG_WRITE 68 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); DPU_REG_WRITE 69 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); DPU_REG_WRITE 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); DPU_REG_WRITE 71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); DPU_REG_WRITE 72 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_START_POS, te->start_pos); DPU_REG_WRITE 73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_SYNC_THRESH, DPU_REG_WRITE 76 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, DPU_REG_WRITE 107 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); DPU_REG_WRITE 128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); DPU_REG_WRITE 191 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); DPU_REG_WRITE 212 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); DPU_REG_WRITE 230 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); DPU_REG_WRITE 302 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_REG_WRITE 307 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_REG_WRITE 331 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, format_off + idx, src_format); DPU_REG_WRITE 332 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); DPU_REG_WRITE 333 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, op_mode_off + idx, opmode); DPU_REG_WRITE 336 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); DPU_REG_WRITE 379 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); DPU_REG_WRITE 380 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); DPU_REG_WRITE 381 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, DPU_REG_WRITE 385 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); DPU_REG_WRITE 386 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); DPU_REG_WRITE 387 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, DPU_REG_WRITE 391 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); DPU_REG_WRITE 392 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); DPU_REG_WRITE 393 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, DPU_REG_WRITE 488 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, src_size_off + idx, src_size); DPU_REG_WRITE 489 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, src_xy_off + idx, src_xy); DPU_REG_WRITE 490 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, out_size_off + idx, dst_size); DPU_REG_WRITE 491 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); DPU_REG_WRITE 493 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); DPU_REG_WRITE 494 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); DPU_REG_WRITE 509 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, DPU_REG_WRITE 512 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, DPU_REG_WRITE 514 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, DPU_REG_WRITE 517 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, DPU_REG_WRITE 519 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, DPU_REG_WRITE 550 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); DPU_REG_WRITE 552 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, DPU_REG_WRITE 564 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); DPU_REG_WRITE 565 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); DPU_REG_WRITE 577 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); DPU_REG_WRITE 578 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, DPU_REG_WRITE 581 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); DPU_REG_WRITE 607 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); DPU_REG_WRITE 631 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(&ctx->hw, SSPP_CDP_CNTL, cdp_cntl); DPU_REG_WRITE 86 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); DPU_REG_WRITE 87 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); DPU_REG_WRITE 88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); DPU_REG_WRITE 89 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); DPU_REG_WRITE 118 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, reg_off, new_val); DPU_REG_WRITE 176 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); DPU_REG_WRITE 209 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, wd_load_value, DPU_REG_WRITE 212 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ DPU_REG_WRITE 216 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, wd_ctl2, reg); DPU_REG_WRITE 265 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static); DPU_REG_WRITE 277 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); DPU_REG_WRITE 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, DPU_REG_WRITE 155 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); DPU_REG_WRITE 193 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); DPU_REG_WRITE 194 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); DPU_REG_WRITE 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); DPU_REG_WRITE 196 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); DPU_REG_WRITE 197 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); DPU_REG_WRITE 198 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b); DPU_REG_WRITE 199 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c); DPU_REG_WRITE 255 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init); DPU_REG_WRITE 257 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset, DPU_REG_WRITE 259 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset, DPU_REG_WRITE 261 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset, DPU_REG_WRITE 263 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset, DPU_REG_WRITE 267 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset, DPU_REG_WRITE 270 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset, DPU_REG_WRITE 273 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset, DPU_REG_WRITE 276 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset, DPU_REG_WRITE 279 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload); DPU_REG_WRITE 281 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb); DPU_REG_WRITE 283 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv); DPU_REG_WRITE 285 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst); DPU_REG_WRITE 299 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode); DPU_REG_WRITE 319 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off, val); DPU_REG_WRITE 322 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x4, val); DPU_REG_WRITE 325 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x8, val); DPU_REG_WRITE 328 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0xc, val); DPU_REG_WRITE 330 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x10, val); DPU_REG_WRITE 334 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x14, val); DPU_REG_WRITE 336 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x18, val); DPU_REG_WRITE 338 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); DPU_REG_WRITE 342 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x20, val); DPU_REG_WRITE 344 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x24, val); DPU_REG_WRITE 346 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x28, val); DPU_REG_WRITE 349 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); DPU_REG_WRITE 350 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); DPU_REG_WRITE 351 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); DPU_REG_WRITE 354 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); DPU_REG_WRITE 355 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); DPU_REG_WRITE 356 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); DPU_REG_WRITE 52 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); DPU_REG_WRITE 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); DPU_REG_WRITE 103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); DPU_REG_WRITE 141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); DPU_REG_WRITE 180 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); DPU_REG_WRITE 181 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl); DPU_REG_WRITE 196 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);