DPU_REG_READ       71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	return DPU_REG_READ(c, CTL_FLUSH);
DPU_REG_READ      238 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		status = DPU_REG_READ(c, CTL_SW_RESET);
DPU_REG_READ      264 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	status = DPU_REG_READ(c, CTL_SW_RESET);
DPU_REG_READ      995 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
DPU_REG_READ      999 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
DPU_REG_READ     1050 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	intr_status = DPU_REG_READ(&intr->hw,
DPU_REG_READ       97 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
DPU_REG_READ      209 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
DPU_REG_READ      227 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
DPU_REG_READ      229 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
DPU_REG_READ      230 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
DPU_REG_READ      246 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	return DPU_REG_READ(c, INTF_LINE_COUNT);
DPU_REG_READ       70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	op_mode = DPU_REG_READ(c, LM_OP_MODE);
DPU_REG_READ      143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	op_mode = DPU_REG_READ(c, LM_OP_MODE);
DPU_REG_READ      122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
DPU_REG_READ      144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
DPU_REG_READ      147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
DPU_REG_READ      151 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	val = DPU_REG_READ(c, PP_LINE_COUNT);
DPU_REG_READ      167 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
DPU_REG_READ      168 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
DPU_REG_READ      173 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 	line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
DPU_REG_READ      183 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 		mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx);
DPU_REG_READ      205 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
DPU_REG_READ      224 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx);
DPU_REG_READ      261 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	opmode = DPU_REG_READ(c, op_mode_off + idx);
DPU_REG_READ      469 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 		ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx);
DPU_REG_READ      470 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 		ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx);
DPU_REG_READ      111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	reg_val = DPU_REG_READ(c, reg_off);
DPU_REG_READ      137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	value = DPU_REG_READ(c, DANGER_STATUS);
DPU_REG_READ      166 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	reg = DPU_REG_READ(c, MDP_VSYNC_SEL);
DPU_REG_READ      213 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 		reg = DPU_REG_READ(c, wd_ctl2);
DPU_REG_READ      234 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	value = DPU_REG_READ(c, SAFE_STATUS);
DPU_REG_READ      305 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
DPU_REG_READ       44 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR);
DPU_REG_READ       45 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR);
DPU_REG_READ       79 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, reg_off);
DPU_REG_READ      100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, reg_off);
DPU_REG_READ      122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, reg_off);
DPU_REG_READ      134 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);
DPU_REG_READ      150 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);
DPU_REG_READ      169 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
DPU_REG_READ      170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high);
DPU_REG_READ      194 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);