DPLL_VGA_MODE_DIS  226 drivers/gpu/drm/gma500/cdv_intel_display.c 	REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
DPLL_VGA_MODE_DIS  663 drivers/gpu/drm/gma500/cdv_intel_display.c 	dpll = DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS  726 drivers/gpu/drm/gma500/cdv_intel_display.c 	REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
DPLL_VGA_MODE_DIS  523 drivers/gpu/drm/gma500/oaktrail_crtc.c 	dpll |= DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS  152 drivers/gpu/drm/gma500/psb_intel_display.c 	dpll = DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 1468 drivers/gpu/drm/i915/display/intel_display.c 		WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
DPLL_VGA_MODE_DIS 1502 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
DPLL_VGA_MODE_DIS 1542 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
DPLL_VGA_MODE_DIS 1554 drivers/gpu/drm/i915/display/intel_display.c 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 1571 drivers/gpu/drm/i915/display/intel_display.c 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 7708 drivers/gpu/drm/i915/display/intel_display.c 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 7725 drivers/gpu/drm/i915/display/intel_display.c 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 8007 drivers/gpu/drm/i915/display/intel_display.c 	dpll = DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 8081 drivers/gpu/drm/i915/display/intel_display.c 	dpll = DPLL_VGA_MODE_DIS;
DPLL_VGA_MODE_DIS 16306 drivers/gpu/drm/i915/display/intel_display.c 		DPLL_VGA_MODE_DIS |
DPLL_VGA_MODE_DIS 16328 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
DPLL_VGA_MODE_DIS 16373 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
DPLL_VGA_MODE_DIS 1183 drivers/gpu/drm/i915/display/intel_display_power.c 		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;