DPLL_VCO_ENABLE 762 drivers/gpu/drm/gma500/cdv_intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 772 drivers/gpu/drm/gma500/cdv_intel_display.c (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 216 drivers/gpu/drm/gma500/gma_display.c if ((temp & DPLL_VCO_ENABLE) == 0) { DPLL_VCO_ENABLE 221 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 225 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 302 drivers/gpu/drm/gma500/gma_display.c if ((temp & DPLL_VCO_ENABLE) != 0) { DPLL_VCO_ENABLE 303 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 582 drivers/gpu/drm/gma500/gma_display.c if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 584 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 253 drivers/gpu/drm/gma500/mdfld_device.c dpll_val &= ~DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 257 drivers/gpu/drm/gma500/mdfld_device.c dpll_val &= ~DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 273 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); DPLL_VCO_ENABLE 281 drivers/gpu/drm/gma500/mdfld_device.c if (!(dpll & DPLL_VCO_ENABLE)) { DPLL_VCO_ENABLE 297 drivers/gpu/drm/gma500/mdfld_device.c dpll_val |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 267 drivers/gpu/drm/gma500/mdfld_intel_display.c if (temp & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 271 drivers/gpu/drm/gma500/mdfld_intel_display.c temp &= ~(DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 324 drivers/gpu/drm/gma500/mdfld_intel_display.c if ((temp & DPLL_VCO_ENABLE) == 0) { DPLL_VCO_ENABLE 339 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 453 drivers/gpu/drm/gma500/mdfld_intel_display.c if (temp & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 457 drivers/gpu/drm/gma500/mdfld_intel_display.c temp &= ~(DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 917 drivers/gpu/drm/gma500/mdfld_intel_display.c if (dpll & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 918 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll &= ~DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 984 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 243 drivers/gpu/drm/gma500/oaktrail_crtc.c if ((temp & DPLL_VCO_ENABLE) == 0) { DPLL_VCO_ENABLE 249 drivers/gpu/drm/gma500/oaktrail_crtc.c temp | DPLL_VCO_ENABLE, i); DPLL_VCO_ENABLE 254 drivers/gpu/drm/gma500/oaktrail_crtc.c temp | DPLL_VCO_ENABLE, i); DPLL_VCO_ENABLE 315 drivers/gpu/drm/gma500/oaktrail_crtc.c if ((temp & DPLL_VCO_ENABLE) != 0) { DPLL_VCO_ENABLE 317 drivers/gpu/drm/gma500/oaktrail_crtc.c temp & ~DPLL_VCO_ENABLE, i); DPLL_VCO_ENABLE 526 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 550 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 552 drivers/gpu/drm/gma500/oaktrail_crtc.c if (dpll & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 555 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); DPLL_VCO_ENABLE 203 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 212 drivers/gpu/drm/gma500/psb_intel_display.c if (dpll & DPLL_VCO_ENABLE) { DPLL_VCO_ENABLE 214 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 1096 drivers/gpu/drm/i915/display/intel_display.c cur_state = !!(val & DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 1400 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) DPLL_VCO_ENABLE 1449 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) DPLL_VCO_ENABLE 7714 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | DPLL_VCO_ENABLE 7731 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 7750 drivers/gpu/drm/i915/display/intel_display.c ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); DPLL_VCO_ENABLE 7753 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) DPLL_VCO_ENABLE 7851 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 7854 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) DPLL_VCO_ENABLE 8060 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 8116 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 8572 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) DPLL_VCO_ENABLE 8683 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) DPLL_VCO_ENABLE 8925 drivers/gpu/drm/i915/display/intel_display.c if (!(temp & DPLL_VCO_ENABLE)) DPLL_VCO_ENABLE 9626 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 16310 drivers/gpu/drm/i915/display/intel_display.c DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 1341 drivers/gpu/drm/i915/display/intel_display_power.c (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) DPLL_VCO_ENABLE 755 drivers/gpu/drm/i915/display/intel_dp.c pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 387 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return val & DPLL_VCO_ENABLE; DPLL_VCO_ENABLE 1336 drivers/video/fbdev/intelfb/intelfbdrv.c OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); DPLL_VCO_ENABLE 1108 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); DPLL_VCO_ENABLE 1399 drivers/video/fbdev/intelfb/intelfbhw.c tmp &= ~DPLL_VCO_ENABLE;