DPLL_STATUS       297 drivers/gpu/drm/gma500/oaktrail_hdmi.c 		REG_WRITE(DPLL_STATUS, 0x1);
DPLL_STATUS       423 drivers/gpu/drm/gma500/oaktrail_hdmi.c 			REG_WRITE(DPLL_STATUS, 0x1);
DPLL_STATUS      1018 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5))
DPLL_STATUS       224 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
DPLL_STATUS      2906 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);