DPLL             1095 drivers/gpu/drm/i915/display/intel_display.c 	val = I915_READ(DPLL(pipe));
DPLL             1381 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
DPLL             1382 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             1385 drivers/gpu/drm/i915/display/intel_display.c 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
DPLL             1431 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
DPLL             1434 drivers/gpu/drm/i915/display/intel_display.c 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
DPLL             1468 drivers/gpu/drm/i915/display/intel_display.c 		WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
DPLL             1487 drivers/gpu/drm/i915/display/intel_display.c 	i915_reg_t reg = DPLL(crtc->pipe);
DPLL             1542 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
DPLL             1543 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             1558 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), val);
DPLL             1559 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             1575 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), val);
DPLL             1576 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             1598 drivers/gpu/drm/i915/display/intel_display.c 		dpll_reg = DPLL(0);
DPLL             1602 drivers/gpu/drm/i915/display/intel_display.c 		dpll_reg = DPLL(0);
DPLL             7748 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe),
DPLL             7850 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe),
DPLL             8840 drivers/gpu/drm/i915/display/intel_display.c 		tmp = I915_READ(DPLL(crtc->pipe));
DPLL             8850 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
DPLL             16328 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
DPLL             16329 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), dpll);
DPLL             16332 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             16340 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), dpll);
DPLL             16344 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(DPLL(pipe), dpll);
DPLL             16345 drivers/gpu/drm/i915/display/intel_display.c 		POSTING_READ(DPLL(pipe));
DPLL             16373 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
DPLL             16374 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(DPLL(pipe));
DPLL             1181 drivers/gpu/drm/i915/display/intel_display_power.c 		u32 val = I915_READ(DPLL(pipe));
DPLL             1187 drivers/gpu/drm/i915/display/intel_display_power.c 		I915_WRITE(DPLL(pipe), val);
DPLL             1341 drivers/gpu/drm/i915/display/intel_display_power.c 		    (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
DPLL             4765 drivers/gpu/drm/i915/display/intel_display_power.c 		u32 status = I915_READ(DPLL(PIPE_A));
DPLL              755 drivers/gpu/drm/i915/display/intel_dp.c 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
DPLL              484 drivers/gpu/drm/i915/display/intel_dvo.c 			dpll[pipe] = I915_READ(DPLL(pipe));
DPLL              485 drivers/gpu/drm/i915/display/intel_dvo.c 			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
DPLL              492 drivers/gpu/drm/i915/display/intel_dvo.c 			I915_WRITE(DPLL(pipe), dpll[pipe]);