DPIO_PHY1 1313 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->chv_phy_assert[DPIO_PHY1]) DPIO_PHY1 1314 drivers/gpu/drm/i915/display/intel_display_power.c phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | DPIO_PHY1 1315 drivers/gpu/drm/i915/display/intel_display_power.c PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | DPIO_PHY1 1316 drivers/gpu/drm/i915/display/intel_display_power.c PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); DPIO_PHY1 1360 drivers/gpu/drm/i915/display/intel_display_power.c phy_status |= PHY_POWERGOOD(DPIO_PHY1); DPIO_PHY1 1363 drivers/gpu/drm/i915/display/intel_display_power.c if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) DPIO_PHY1 1364 drivers/gpu/drm/i915/display/intel_display_power.c phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); DPIO_PHY1 1367 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) DPIO_PHY1 1368 drivers/gpu/drm/i915/display/intel_display_power.c phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); DPIO_PHY1 1371 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) DPIO_PHY1 1372 drivers/gpu/drm/i915/display/intel_display_power.c phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); DPIO_PHY1 1374 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) DPIO_PHY1 1375 drivers/gpu/drm/i915/display/intel_display_power.c phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); DPIO_PHY1 1408 drivers/gpu/drm/i915/display/intel_display_power.c phy = DPIO_PHY1; DPIO_PHY1 1467 drivers/gpu/drm/i915/display/intel_display_power.c phy = DPIO_PHY1; DPIO_PHY1 3044 drivers/gpu/drm/i915/display/intel_display_power.c .bxt.phy = DPIO_PHY1, DPIO_PHY1 3104 drivers/gpu/drm/i915/display/intel_display_power.c .bxt.phy = DPIO_PHY1, DPIO_PHY1 4752 drivers/gpu/drm/i915/display/intel_display_power.c PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | DPIO_PHY1 4755 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); DPIO_PHY1 4805 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); DPIO_PHY1 4808 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); DPIO_PHY1 4810 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); DPIO_PHY1 4812 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY1] = false; DPIO_PHY1 4814 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY1] = true; DPIO_PHY1 1319 drivers/gpu/drm/i915/display/intel_display_types.h return DPIO_PHY1; DPIO_PHY1 163 drivers/gpu/drm/i915/display/intel_dpio_phy.c .rcomp_phy = DPIO_PHY1, DPIO_PHY1 171 drivers/gpu/drm/i915/display/intel_dpio_phy.c [DPIO_PHY1] = { DPIO_PHY1 185 drivers/gpu/drm/i915/display/intel_dpio_phy.c .rcomp_phy = DPIO_PHY1, DPIO_PHY1 193 drivers/gpu/drm/i915/display/intel_dpio_phy.c [DPIO_PHY1] = { DPIO_PHY1 205 drivers/gpu/drm/i915/display/intel_dpio_phy.c .rcomp_phy = DPIO_PHY1, DPIO_PHY1 1616 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= DPIO_PHY1 1618 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= DPIO_PHY1 3146 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, DPIO_PHY1 3168 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); DPIO_PHY1 3169 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); DPIO_PHY1 3170 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); DPIO_PHY1 3171 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); DPIO_PHY1 3172 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); DPIO_PHY1 3173 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); DPIO_PHY1 3174 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); DPIO_PHY1 3175 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); DPIO_PHY1 3176 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); DPIO_PHY1 3234 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3235 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3236 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3237 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3238 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3239 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3240 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, DPIO_PHY1 3242 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3243 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3244 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, DPIO_PHY1 3246 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3247 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3248 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); DPIO_PHY1 3249 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); DPIO_PHY1 3250 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); DPIO_PHY1 3251 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); DPIO_PHY1 3252 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); DPIO_PHY1 3253 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); DPIO_PHY1 3254 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); DPIO_PHY1 3255 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); DPIO_PHY1 3256 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); DPIO_PHY1 3257 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); DPIO_PHY1 3258 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); DPIO_PHY1 3259 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); DPIO_PHY1 3260 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); DPIO_PHY1 253 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= DPIO_PHY1 257 drivers/gpu/drm/i915/gvt/mmio.c vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= DPIO_PHY1 456 drivers/gpu/drm/i915/i915_drv.c DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;