DPIO_CH1         1309 drivers/gpu/drm/i915/display/intel_display_power.c 				     PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
DPIO_CH1         1310 drivers/gpu/drm/i915/display/intel_display_power.c 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
DPIO_CH1         1311 drivers/gpu/drm/i915/display/intel_display_power.c 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
DPIO_CH1         1325 drivers/gpu/drm/i915/display/intel_display_power.c 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
DPIO_CH1         1326 drivers/gpu/drm/i915/display/intel_display_power.c 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
DPIO_CH1         1331 drivers/gpu/drm/i915/display/intel_display_power.c 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
DPIO_CH1         1340 drivers/gpu/drm/i915/display/intel_display_power.c 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
DPIO_CH1         1342 drivers/gpu/drm/i915/display/intel_display_power.c 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
DPIO_CH1         1352 drivers/gpu/drm/i915/display/intel_display_power.c 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
DPIO_CH1         1353 drivers/gpu/drm/i915/display/intel_display_power.c 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
DPIO_CH1         1355 drivers/gpu/drm/i915/display/intel_display_power.c 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
DPIO_CH1         1356 drivers/gpu/drm/i915/display/intel_display_power.c 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
DPIO_CH1         1526 drivers/gpu/drm/i915/display/intel_display_power.c 		if (ch == DPIO_CH1 && val == 0)
DPIO_CH1         4754 drivers/gpu/drm/i915/display/intel_display_power.c 		PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
DPIO_CH1         4783 drivers/gpu/drm/i915/display/intel_display_power.c 				PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
DPIO_CH1         4786 drivers/gpu/drm/i915/display/intel_display_power.c 			PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
DPIO_CH1         1305 drivers/gpu/drm/i915/display/intel_display_types.h 		return DPIO_CH1;
DPIO_CH1         1333 drivers/gpu/drm/i915/display/intel_display_types.h 		return DPIO_CH1;
DPIO_CH1          168 drivers/gpu/drm/i915/display/intel_dpio_phy.c 			[DPIO_CH1] = { .port = PORT_C },
DPIO_CH1          255 drivers/gpu/drm/i915/display/intel_dpio_phy.c 		    port == phy_info->channel[DPIO_CH1].port) {
DPIO_CH1          257 drivers/gpu/drm/i915/display/intel_dpio_phy.c 			*ch = DPIO_CH1;
DPIO_CH1          799 drivers/gpu/drm/i915/display/intel_dpio_phy.c 			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
DPIO_CH1          814 drivers/gpu/drm/i915/display/intel_dpio_phy.c 		if (ch == DPIO_CH1)
DPIO_CH1          822 drivers/gpu/drm/i915/display/intel_dpio_phy.c 		if (ch == DPIO_CH1)
DPIO_CH1          947 drivers/gpu/drm/i915/display/intel_dpio_phy.c 		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
DPIO_CH1         3206 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3207 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3208 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3209 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3210 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3211 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3212 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
DPIO_CH1         3214 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3215 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3216 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
DPIO_CH1         3218 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3219 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3220 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
DPIO_CH1         3221 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
DPIO_CH1         3222 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
DPIO_CH1         3223 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
DPIO_CH1         3224 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
DPIO_CH1         3225 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
DPIO_CH1         3226 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
DPIO_CH1         3227 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
DPIO_CH1         3228 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
DPIO_CH1         3229 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
DPIO_CH1         3230 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
DPIO_CH1         3231 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
DPIO_CH1         3232 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);