DPG_WATERMARK_MASK_CONTROL 1120 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
DPG_WATERMARK_MASK_CONTROL 1127 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
DPG_WATERMARK_MASK_CONTROL 1146 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
DPG_WATERMARK_MASK_CONTROL 1153 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
DPG_WATERMARK_MASK_CONTROL  169 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL  183 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL  202 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL  215 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL  234 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL  252 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
DPG_WATERMARK_MASK_CONTROL   52 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
DPG_WATERMARK_MASK_CONTROL  107 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	uint32_t DPG_WATERMARK_MASK_CONTROL;
DPG_WATERMARK_MASK_CONTROL  177 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
DPG_WATERMARK_MASK_CONTROL  178 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
DPG_WATERMARK_MASK_CONTROL  188 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
DPG_WATERMARK_MASK_CONTROL  222 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
DPG_WATERMARK_MASK_CONTROL 9353 drivers/gpu/drm/radeon/cik.c 	wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
DPG_WATERMARK_MASK_CONTROL 9357 drivers/gpu/drm/radeon/cik.c 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
DPG_WATERMARK_MASK_CONTROL 9362 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
DPG_WATERMARK_MASK_CONTROL 9365 drivers/gpu/drm/radeon/cik.c 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
DPG_WATERMARK_MASK_CONTROL 9370 drivers/gpu/drm/radeon/cik.c 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);