DPG_PIPE_STUTTER_CONTROL 5466 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
DPG_PIPE_STUTTER_CONTROL  242 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL  259 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL  279 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL  308 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL  341 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL   54 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
DPG_PIPE_STUTTER_CONTROL  112 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	uint32_t DPG_PIPE_STUTTER_CONTROL;
DPG_PIPE_STUTTER_CONTROL  181 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
DPG_PIPE_STUTTER_CONTROL  182 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
DPG_PIPE_STUTTER_CONTROL  187 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
DPG_PIPE_STUTTER_CONTROL 1209 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL 1111 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL 1022 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	    && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
DPG_PIPE_STUTTER_CONTROL 1015 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
DPG_PIPE_STUTTER_CONTROL 2932 drivers/gpu/drm/radeon/ci_dpm.c 	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
DPG_PIPE_STUTTER_CONTROL 5004 drivers/gpu/drm/radeon/si_dpm.c 	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&