DOORBELL_EN 398 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); DOORBELL_EN 353 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); DOORBELL_EN 338 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); DOORBELL_EN 299 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); DOORBELL_EN 2797 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 1); DOORBELL_EN 2800 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 0); DOORBELL_EN 3089 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 1); DOORBELL_EN 3092 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 0); DOORBELL_EN 3293 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 1); DOORBELL_EN 3300 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 0); DOORBELL_EN 3360 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c DOORBELL_EN, 1); DOORBELL_EN 4272 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c DOORBELL_EN, 1); DOORBELL_EN 4274 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); DOORBELL_EN 4489 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c DOORBELL_EN, DOORBELL_EN 4542 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c DOORBELL_EN, 1); DOORBELL_EN 3248 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c DOORBELL_EN, 1); DOORBELL_EN 3250 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); DOORBELL_EN 3454 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c DOORBELL_EN, 1); DOORBELL_EN 3461 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c DOORBELL_EN, 0); DOORBELL_EN 3521 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c DOORBELL_EN, 1); DOORBELL_EN 4632 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN; DOORBELL_EN 4634 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN; DOORBELL_EN 4720 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;