DM_PP_MAX_CLOCK_LEVELS  257 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
DM_PP_MAX_CLOCK_LEVELS  261 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				DM_PP_MAX_CLOCK_LEVELS);
DM_PP_MAX_CLOCK_LEVELS  263 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
DM_PP_MAX_CLOCK_LEVELS  283 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
DM_PP_MAX_CLOCK_LEVELS  287 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				DM_PP_MAX_CLOCK_LEVELS);
DM_PP_MAX_CLOCK_LEVELS  289 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
DM_PP_MAX_CLOCK_LEVELS  310 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
DM_PP_MAX_CLOCK_LEVELS  314 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				DM_PP_MAX_CLOCK_LEVELS);
DM_PP_MAX_CLOCK_LEVELS  316 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
DM_PP_MAX_CLOCK_LEVELS   99 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
DM_PP_MAX_CLOCK_LEVELS  109 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
DM_PP_MAX_CLOCK_LEVELS  119 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];