DM_INC             25 arch/sh/drivers/dma/dma-sh.c #define RS_DUAL	(DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))
DM_INC             35 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             45 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             55 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             65 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC             75 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC             85 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
DM_INC             41 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             51 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             61 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             71 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             81 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC             91 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
DM_INC            101 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC            111 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC            121 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC            131 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
DM_INC            141 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
DM_INC            151 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
DM_INC            127 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            141 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            158 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            172 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            186 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            200 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            217 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            231 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            245 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            259 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            273 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            290 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            304 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            318 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            332 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC            346 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
DM_INC             46 drivers/dma/sh/shdma-arm.h #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
DM_INC            239 drivers/dma/sh/shdmac.c 	u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,