DMCU_SF            78 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_CTRL, \
DMCU_SF            80 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_STATUS, \
DMCU_SF            82 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_STATUS, \
DMCU_SF            84 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF            86 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF            88 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF            90 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CMD_REG, \
DMCU_SF            92 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
DMCU_SF            93 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
DMCU_SF            95 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
DMCU_SF            97 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
DMCU_SF            99 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
DMCU_SF           101 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
DMCU_SF           104 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_CTRL, \
DMCU_SF           106 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_STATUS, \
DMCU_SF           108 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_STATUS, \
DMCU_SF           110 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF           112 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF           114 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
DMCU_SF           116 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CMD_REG, \
DMCU_SF           118 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
DMCU_SF           119 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
DMCU_SF           123 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DCI_MEM_PWR_STATUS, \
DMCU_SF           128 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMU_MEM_PWR_CNTL, \