DMA_RB_WPTR        51 drivers/gpu/drm/amd/amdgpu/si_dma.c 	return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
DMA_RB_WPTR        59 drivers/gpu/drm/amd/amdgpu/si_dma.c 	WREG32(DMA_RB_WPTR + sdma_offsets[me],
DMA_RB_WPTR       154 drivers/gpu/drm/amd/amdgpu/si_dma.c 		WREG32(DMA_RB_WPTR + sdma_offsets[i], 0);
DMA_RB_WPTR       177 drivers/gpu/drm/amd/amdgpu/si_dma.c 		WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
DMA_RB_WPTR        86 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
DMA_RB_WPTR        88 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
DMA_RB_WPTR       107 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
DMA_RB_WPTR       109 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
DMA_RB_WPTR       219 drivers/gpu/drm/radeon/ni_dma.c 		WREG32(DMA_RB_WPTR + reg_offset, 0);
DMA_RB_WPTR       244 drivers/gpu/drm/radeon/ni_dma.c 		WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
DMA_RB_WPTR        75 drivers/gpu/drm/radeon/r600_dma.c 	return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
DMA_RB_WPTR        89 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
DMA_RB_WPTR       140 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_WPTR, 0);
DMA_RB_WPTR       168 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_WPTR, ring->wptr << 2);