DMA_RB_CNTL       121 drivers/gpu/drm/amd/amdgpu/si_dma.c 		rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
DMA_RB_CNTL       123 drivers/gpu/drm/amd/amdgpu/si_dma.c 		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
DMA_RB_CNTL       150 drivers/gpu/drm/amd/amdgpu/si_dma.c 		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
DMA_RB_CNTL       178 drivers/gpu/drm/amd/amdgpu/si_dma.c 		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);
DMA_RB_CNTL      3913 drivers/gpu/drm/radeon/evergreen.c 		tmp = RREG32(DMA_RB_CNTL);
DMA_RB_CNTL      3915 drivers/gpu/drm/radeon/evergreen.c 		WREG32(DMA_RB_CNTL, tmp);
DMA_RB_CNTL      4022 drivers/gpu/drm/radeon/evergreen.c 	tmp = RREG32(DMA_RB_CNTL);
DMA_RB_CNTL      4024 drivers/gpu/drm/radeon/evergreen.c 	WREG32(DMA_RB_CNTL, tmp);
DMA_RB_CNTL      1850 drivers/gpu/drm/radeon/ni.c 		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
DMA_RB_CNTL      1852 drivers/gpu/drm/radeon/ni.c 		WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
DMA_RB_CNTL      1857 drivers/gpu/drm/radeon/ni.c 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA_RB_CNTL      1859 drivers/gpu/drm/radeon/ni.c 		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA_RB_CNTL       166 drivers/gpu/drm/radeon/ni_dma.c 	rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
DMA_RB_CNTL       168 drivers/gpu/drm/radeon/ni_dma.c 	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
DMA_RB_CNTL       171 drivers/gpu/drm/radeon/ni_dma.c 	rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA_RB_CNTL       173 drivers/gpu/drm/radeon/ni_dma.c 	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
DMA_RB_CNTL       215 drivers/gpu/drm/radeon/ni_dma.c 		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
DMA_RB_CNTL       246 drivers/gpu/drm/radeon/ni_dma.c 		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
DMA_RB_CNTL      1709 drivers/gpu/drm/radeon/r600.c 		tmp = RREG32(DMA_RB_CNTL);
DMA_RB_CNTL      1711 drivers/gpu/drm/radeon/r600.c 		WREG32(DMA_RB_CNTL, tmp);
DMA_RB_CNTL      1840 drivers/gpu/drm/radeon/r600.c 	tmp = RREG32(DMA_RB_CNTL);
DMA_RB_CNTL      1842 drivers/gpu/drm/radeon/r600.c 	WREG32(DMA_RB_CNTL, tmp);
DMA_RB_CNTL       101 drivers/gpu/drm/radeon/r600_dma.c 	u32 rb_cntl = RREG32(DMA_RB_CNTL);
DMA_RB_CNTL       107 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_CNTL, rb_cntl);
DMA_RB_CNTL       136 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_CNTL, rb_cntl);
DMA_RB_CNTL       170 drivers/gpu/drm/radeon/r600_dma.c 	WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
DMA_RB_CNTL      3884 drivers/gpu/drm/radeon/si.c 		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
DMA_RB_CNTL      3886 drivers/gpu/drm/radeon/si.c 		WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
DMA_RB_CNTL      3890 drivers/gpu/drm/radeon/si.c 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA_RB_CNTL      3892 drivers/gpu/drm/radeon/si.c 		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA_RB_CNTL      4051 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
DMA_RB_CNTL      4053 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
DMA_RB_CNTL      4055 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA_RB_CNTL      4057 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);