DMA_DS            128 arch/mips/alchemy/common/dma.c 	{ AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 },		/* coherent */
DMA_DS            129 arch/mips/alchemy/common/dma.c 	{ AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR },	/* coherent */
DMA_DS            130 arch/mips/alchemy/common/dma.c 	{ AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 },		/* coherent */
DMA_DS            131 arch/mips/alchemy/common/dma.c 	{ AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }	/* coherent */
DMA_DS            301 arch/mips/include/asm/mach-au1x00/au1000_dma.h 	if (chan->mode & DMA_DS)	/* second bank of device IDs */