DMA_DR             82 arch/mips/alchemy/common/dma.c 	{ AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR },	/* UART0_RX */
DMA_DR             86 arch/mips/alchemy/common/dma.c 	{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR },	/* AC97 RX c */
DMA_DR             88 arch/mips/alchemy/common/dma.c 	{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
DMA_DR             89 arch/mips/alchemy/common/dma.c 	{ AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
DMA_DR             93 arch/mips/alchemy/common/dma.c 	{ AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
DMA_DR             94 arch/mips/alchemy/common/dma.c 	{ AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
DMA_DR             97 arch/mips/alchemy/common/dma.c 	{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
DMA_DR            129 arch/mips/alchemy/common/dma.c 	{ AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR },	/* coherent */
DMA_DR            131 arch/mips/alchemy/common/dma.c 	{ AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }	/* coherent */
DMA_DR            266 arch/mips/include/asm/mach-au1x00/au1000_dma.h 	mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
DMA_DR            267 arch/mips/include/asm/mach-au1x00/au1000_dma.h 	chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);