DMAC1              42 arch/sh/kernel/cpu/sh2/setup-sh7619.c 	INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
DMAC1              53 arch/sh/kernel/cpu/sh2/setup-sh7619.c 	{ 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
DMAC1              53 arch/sh/kernel/cpu/sh2a/setup-sh7203.c 	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
DMAC1             140 arch/sh/kernel/cpu/sh2a/setup-sh7203.c 	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
DMAC1              52 arch/sh/kernel/cpu/sh2a/setup-sh7206.c 	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
DMAC1             109 arch/sh/kernel/cpu/sh2a/setup-sh7206.c 	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
DMAC1              60 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
DMAC1             193 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1,  DMAC2,  DMAC3 } },
DMAC1              64 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
DMAC1             210 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1, DMAC2,  DMAC3 } },
DMAC1              32 arch/sh/kernel/cpu/sh3/setup-sh7710.c 	INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
DMAC1              33 arch/sh/kernel/cpu/sh3/setup-sh7710.c 	INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
DMAC1              61 arch/sh/kernel/cpu/sh3/setup-sh7710.c 	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
DMAC1             244 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1, 0x800),
DMAC1             245 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(DMAC1, 0x820),      INTC_VECT(DMAC1, 0x840),
DMAC1             246 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(DMAC1, 0x860),      INTC_VECT(LCDC, 0x900),
DMAC1             270 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
DMAC1             338 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
DMAC1             367 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
DMAC1             381 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
DMAC1             279 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
DMAC1             305 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
DMAC1             318 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
DMAC1             555 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
DMAC1             582 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
DMAC1             595 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
DMAC1             326 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
DMAC1             338 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
DMAC1             339 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
DMAC1             358 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	    PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
DMAC1             367 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
DMAC1             404 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
DMAC1             405 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
DMAC1             406 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
DMAC1             407 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_VECT(DMAC1, 0x940),
DMAC1             454 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	    PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
DMAC1             467 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
DMAC1             251 arch/sh/kernel/cpu/sh4a/setup-shx3.c 	INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
DMAC1             295 arch/sh/kernel/cpu/sh4a/setup-shx3.c 	{ 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,