DMA1_REGISTER_OFFSET 1718 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
DMA1_REGISTER_OFFSET   33 drivers/gpu/drm/amd/amdgpu/si_dma.c 	DMA1_REGISTER_OFFSET
DMA1_REGISTER_OFFSET  613 drivers/gpu/drm/amd/amdgpu/si_dma.c 			sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET  615 drivers/gpu/drm/amd/amdgpu/si_dma.c 			WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
DMA1_REGISTER_OFFSET  618 drivers/gpu/drm/amd/amdgpu/si_dma.c 			sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET  620 drivers/gpu/drm/amd/amdgpu/si_dma.c 			WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
DMA1_REGISTER_OFFSET  658 drivers/gpu/drm/amd/amdgpu/si_dma.c 				offset = DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET  670 drivers/gpu/drm/amd/amdgpu/si_dma.c 				offset = DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET  871 drivers/gpu/drm/radeon/ni.c 	case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
DMA1_REGISTER_OFFSET 1133 drivers/gpu/drm/radeon/ni.c 	WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
DMA1_REGISTER_OFFSET 1774 drivers/gpu/drm/radeon/ni.c 	tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET 1857 drivers/gpu/drm/radeon/ni.c 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET 1859 drivers/gpu/drm/radeon/ni.c 		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA1_REGISTER_OFFSET   64 drivers/gpu/drm/radeon/ni_dma.c 			reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET   88 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET  109 drivers/gpu/drm/radeon/ni_dma.c 		reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET  171 drivers/gpu/drm/radeon/ni_dma.c 	rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET  173 drivers/gpu/drm/radeon/ni_dma.c 	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
DMA1_REGISTER_OFFSET  202 drivers/gpu/drm/radeon/ni_dma.c 			reg_offset = DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET 1323 drivers/gpu/drm/radeon/si.c 	case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
DMA1_REGISTER_OFFSET 3283 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
DMA1_REGISTER_OFFSET 3807 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET 3890 drivers/gpu/drm/radeon/si.c 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET 3892 drivers/gpu/drm/radeon/si.c 		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA1_REGISTER_OFFSET 4055 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
DMA1_REGISTER_OFFSET 4057 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA1_REGISTER_OFFSET 5541 drivers/gpu/drm/radeon/si.c 				offset = DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET 5553 drivers/gpu/drm/radeon/si.c 				offset = DMA1_REGISTER_OFFSET;
DMA1_REGISTER_OFFSET 5960 drivers/gpu/drm/radeon/si.c 	tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
DMA1_REGISTER_OFFSET 5961 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
DMA1_REGISTER_OFFSET 6075 drivers/gpu/drm/radeon/si.c 	dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
DMA1_REGISTER_OFFSET 6108 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);